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ADC9708CMJ bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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4 / 8 page Test Circuits (Continued) TLH10409 – 9 FIGURE 3 LinearityAcquisition Time Conversion Time Test Circuit TLH10409 – 10 FIGURE 4 Static Measurements Functional Description This Analog to Digital Converter is a single-slope 8-bit 6-channel AD converter that provides all of the necessary analog functions for a microprocessor-based datacontrol system The device uses the processor system to provide the necessary addressing timing and counting functions and includes a 1-of-8 decoder 8-channel analog multiplex- er sample and hold precision current reference ramp inte- grator and comparator on a single monolithic chip Applications that require auto-zero or auto-calibration (See Figures 5 – 8 ) can use selection of address 000 and 111 for input address lines A0 – A2 in conjunction with the arithme- tic capability of a microprocessor to provide ground and scaling factors Address 0 0 0 internally connects the input of the ramp generator to ground and may be used for zero offset correction in subsequent conversions Address 1 1 1 internally connects the input of the ramp generator to the voltage reference VREF and may be used for scale factor correction in subsequent conversions For the following re- fer to the Functional Block Diagram Six separate external analog voltage inputs may come into terminals I1 – I6 and the specific analog input to be convert- ed is selected via address terminals A0 – A2 The analog input voltage level is transferred to the external ramp capac- itor connected to pin 4 when the input to the ramp start terminal (pin 3) is at a logic 0 (See Figure 1 ) The time to charge the capacitor is the acquisition time which is a func- tion of the output impedance of an amplifier internal to the AD converter and the value of the capacitor After charging the external capacitor the ramp start terminal is switched to a logic 1 which introduces a high impedance between the analog input voltage and the external capacitor The capacitor begins to discharge at a controlled rate The controlled rate of discharge (ramp) is established by the ex- ternal reference voltage the external reference resistor the value of the external capacitor and the internal leakage of the AD converter Connected to the capacitor terminal is a comparator internal to the AD converter with its output go- ing to the ramp stop terminal (pin 7) The comparator output is a logic one when the capacitor is charged and switches to a logic 0 when the capacitor is in a discharged state The ramp time is from the time when ramp start goes HIGH (log- ic ‘‘1’’) to when ramp stop goes LOW (logic ‘‘0’’) The micro- processor must be programmed to determine this conver- sion time The ideal (no undesirable internal source imped- ances leakage paths errors on levels where comparator switches or delay time) conversion time is calculated as fol- lows Ramp Time e V1 CH IR Where V1 e Analog Input Voltage Being Measured CH e External Ramp Capacitor IR e VCC b VREF RREF Where VCC e Power Supply Voltage VREF e Reference Voltage RREF e Reference Resistor In actual use the errors due to a nonideal AD converter can be minimized by using a microprocessor to make the calcu- lations (See Figures 5 through 8 ) Channel Selection Input Address Line Selected A2 A1 A0 Analog Input 0 0 0 Ground 001 I1 010 I2 011 I3 100 I4 101 I5 110 I6 111 VREF 4 |
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