công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

74F112 bảng dữ liệu(PDF) 5 Page - NXP Semiconductors

tên linh kiện 74F112
Giải thích chi tiết về linh kiện  Dual J-K negative edge-triggered flip-flop
Download  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  PHILIPS [NXP Semiconductors]
Trang chủ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F112 bảng dữ liệu(HTML) 5 Page - NXP Semiconductors

  74F112 Datasheet HTML 1Page - NXP Semiconductors 74F112 Datasheet HTML 2Page - NXP Semiconductors 74F112 Datasheet HTML 3Page - NXP Semiconductors 74F112 Datasheet HTML 4Page - NXP Semiconductors 74F112 Datasheet HTML 5Page - NXP Semiconductors 74F112 Datasheet HTML 6Page - NXP Semiconductors 74F112 Datasheet HTML 7Page - NXP Semiconductors 74F112 Datasheet HTML 8Page - NXP Semiconductors 74F112 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 10 page
background image
Philips Semiconductors
Product specification
74F112
Dual J-K negative edge-triggered flip-flop
February 9, 1990
5
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
fMAX
Maximum clock frequency
Waveform 1
85
100
80
80
MHz
tPLH
tPHL
Propagation delay
CP to Qn or Qn
Waveform 1
2.0
2.0
5.0
5.0
6.5
6.5
2.0
2.0
7.5
7.5
2.0
2.0
7.5
7.5
ns
tPLH
tPHL
Propagation delay
SDn, RD to Qn or Qn
Waveform 2,3
2.0
2.0
4.5
4.5
6.5
6.5
2.0
2.0
7.5
7.5
1.5
1.5
7.5
7.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tS(H)
tS((L)
Setup time, High or Low
Jn, Kn to CP
Waveform 1
4.0
3.5
5.0
4.0
5.0
4.0
ns
th(H)
th(L)
Hold time, High or Low
Jn, Kn to CP
Waveform 1
0.0
0.0
0.0
0.0
0.0
0.0
ns
tW(H)
tW(L)
CP Pulse width
High or Low
Waveform 1
4.5
4.5
5.0
5.0
5.0
5.0
ns
tW(L)
SDn, RD Pulse width
Low
Waveform 2,3
4.5
5.0
5.0
ns
tREC
Recovery time
SDn, RD to CP
Waveform 2,3
4.5
5.0
5.0
ns
AC WAVEFORMS
For all waveforms, VM = 1.5V.
VM
VM
CPn
VM
VM
VM
VM
VM
VM
ts(H)
th(H)
Jn, Kn
Qn
VM
tw(L)
fmax
ts(L)
th(L)
VM
VM
tPLH
Qn
tw(H)
tPHL
tPHL
tPLH
SF00107
The shaded areas indicate when the input is permitted to change for predictable output performance.
Waveform 1.
Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width


Số phần tương tự - 74F112

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Fairchild Semiconductor
74F112 FAIRCHILD-74F112 Datasheet
59Kb / 6P
   Dual JK Negative Edge-Triggered Flip-Flop
74F112 FAIRCHILD-74F112 Datasheet
83Kb / 7P
   Dual JK Negative Edge-Triggered Flip-Flop
74F112PC FAIRCHILD-74F112PC Datasheet
59Kb / 6P
   Dual JK Negative Edge-Triggered Flip-Flop
74F112PC FAIRCHILD-74F112PC Datasheet
83Kb / 7P
   Dual JK Negative Edge-Triggered Flip-Flop
74F112SC FAIRCHILD-74F112SC Datasheet
59Kb / 6P
   Dual JK Negative Edge-Triggered Flip-Flop
More results

Mô tả tương tự - 74F112

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
NXP Semiconductors
74ALS112A PHILIPS-74ALS112A Datasheet
92Kb / 10P
   Dual J-K negative edge-triggered flip-flop
1991 Feb 08
logo
Texas Instruments
SN74F112NSR TI1-SN74F112NSR Datasheet
627Kb / 13P
[Old version datasheet]   DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
logo
Mitsubishi Electric Sem...
M74LS73AP MITSUBISHI-M74LS73AP Datasheet
220Kb / 4P
   DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP FLOP WITH RESET
logo
Texas Instruments
CD54AC112 TI1-CD54AC112_14 Datasheet
903Kb / 15P
[Old version datasheet]   DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
logo
Fairchild Semiconductor
DM74ALS109A FAIRCHILD-DM74ALS109A Datasheet
55Kb / 6P
   Dual J-K Positive-Edge-Triggered Flip-Flop
logo
Texas Instruments
SN54LS112A TI1-SN54LS112A_15 Datasheet
1Mb / 20P
[Old version datasheet]   DUAL J-K NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
74ACT11112 TI-74ACT11112 Datasheet
75Kb / 5P
[Old version datasheet]   DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
SN74F112 TI-SN74F112 Datasheet
73Kb / 5P
[Old version datasheet]   DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112A TI-SN74LVC112A Datasheet
292Kb / 13P
[Old version datasheet]   DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
74ACT11112 TI1-74ACT11112_11 Datasheet
214Kb / 8P
[Old version datasheet]   DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
More results


Html Pages

1 2 3 4 5 6 7 8 9 10


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com