9
March 22, 2006
Preliminary
Register 6:
GPIO Interrupt Mask (GPIOIM), offset 0x410 ....................................................................... 105
Register 7:
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................... 106
Register 8:
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ..................................................... 107
Register 9:
GPIO Interrupt Clear (GPIOICR), offset 0x41C .................................................................... 108
Register 10:
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 .............................................. 109
Register 11:
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................... 110
Register 12:
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................... 111
Register 13:
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................... 112
Register 14:
GPIO Open Drain Select (GPIOODR), offset 0x50C ............................................................ 113
Register 15:
GPIO Pull-Up Select (GPIOPUR), offset 0x510.................................................................... 114
Register 16:
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ............................................................... 115
Register 17:
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................... 116
Register 18:
GPIO Digital Input Enable (GPIODEN), offset 0x51C........................................................... 117
Register 19:
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0......................................... 118
Register 20:
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4......................................... 119
Register 21:
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8......................................... 120
Register 22:
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ........................................ 121
Register 23:
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0......................................... 122
Register 24:
GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4.......................................... 123
Register 25:
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8......................................... 124
Register 26:
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ........................................ 125
Register 27:
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0............................................ 126
Register 28:
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4............................................ 127
Register 29:
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8............................................ 128
Register 30:
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ........................................... 129
General-Purpose Timers .............................................................................................................. 130
Register 1:
GPTM Configuration (GPTMCFG), offset 0x000 .................................................................. 141
Register 2:
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................... 142
Register 3:
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................... 143
Register 4:
GPTM Control (GPTMCTL), offset 0x00C ............................................................................ 144
Register 5:
GPTM Interrupt Mask (GPTMIMR), offset 0x018.................................................................. 146
Register 6:
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C........................................................ 147
Register 7:
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020................................................... 148
Register 8:
GPTM Interrupt Clear (GPTMICR), offset 0x024 .................................................................. 149
Register 9:
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028.................................................... 150
Register 10:
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................... 151
Register 11:
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030..................................................... 152
Register 12:
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034..................................................... 153
Register 13:
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................... 154
Register 14:
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................... 155
Register 15:
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ............................................. 156
Register 16:
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ............................................. 157
Register 17:
GPTM TimerA (GPTMTAR), offset 0x048 ............................................................................ 158
Register 18:
GPTM TimerB (GPTMTBR), offset 0x04C............................................................................ 159
Watchdog Timer............................................................................................................................ 160
Register 1:
Watchdog Load (WDTLOAD), offset 0x000.......................................................................... 163
Register 2:
Watchdog Value (WDTVALUE), offset 0x004....................................................................... 164
Register 3:
Watchdog Control (WDTCTL), offset 0x008 ......................................................................... 165
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
