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2 / 12 page Philips Semiconductors Preliminary specification 74ALVCH16952 16-bit registered transceiver (3-State) 2 1998 Sep 01 FEATURES • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through pin-out architecture • Low inductance, multiple center power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • Output drive capability 50Ω transmission lines @ 85°C DESCRIPTION The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bi-directional busses. Data applied to the inputs is entered and stored on the rising edge of the clock (CPXX, where X is AB or BA) provided that the clock enable (CEXX) is LOW. The data is then present at the 3-State output buffers, but is only accessible when the output enable input (OEXX) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay CPnn, to An, Bn VCC = 3.3V, CL = 50pF V 25V C 30pF 3.2 ns fMAX Maximum clock frequency VCC = 2.5V, CL = 30pF 350 MHz CI Input capacitance 3.0 pF CPD Power dissipation capacitance per buffer VI = GND to VCC1 30 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVCH16952 DGG ACH16952 DGG SOT364-1 FUNCTION TABLE for register An or Bn INPUTS INTERNAL OPERATING An or Bn CPXX CEXX Q MODE X X H NC Hold data L ° L L Load data H ° L H Load data H = HIGH voltage level L = LOW voltage level ↑ = LOW-to-HIGH transition FUNCTION TABLE for output enable INPUTS INTERNAL An or Bn OPERATING OEnn Q OUTPUTS MODE H X Z Disable outputs L L L Enable outputs L H H Enable outputs NC = no change X = don’t care Z = high impedance OFF-state |
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