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2 / 11 page Philips Semiconductors Product specification 74ALVCH162244 16-bit buffer/line driver with 30 W termination resistor (3-State) 2 1998 Jun 29 853-2084 19638 FEATURES • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple V CC and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • Bus hold on all data inputs • Integrated 30Ω termination resistor DESCRIPTION The 74ALVCH162244 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74ALVCH162244 is a 16-bit non-inverting buffer/line driver with 3-State outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74ALVCH162244 is designed with 30 Ω series resistors in both HIGH and LOW output states. The 74ALVCH162244 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y1 GND 2Y2 2Y3 3Y0 3Y1 GND 2Y0 3Y2 3Y3 VCC 4Y0 4Y1 4A1 4A0 VCC 3A3 3A2 GND 3A1 3A0 2A3 2A2 GND 2A1 2A0 VCC 1A3 1A2 GND 1A1 1A0 2OE 21 22 23 24 25 26 27 28 GND 4Y2 4Y3 4OE 3OE 4A3 4A2 GND SW00194 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay An to Yn VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF 3.0 2.7 ns CI Input capacitance 5.0 pF C Power dissipation capacitance per buffer V = GND to VCC1 Outputs enabled 25 pF CPD Power dissipation capacitance per buffer VI = GND to VCC1 Outputs disabled 4 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III –40 °C to +85°C 74ALVCH162244 DL ACH162244 DL SOT370-1 48-Pin Plastic TSSOP Type II –40 °C to +85°C 74ALVCH162244 DGG ACH162244 DGG SOT362-1 |
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