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OP15AJMDA bảng dữ liệu(PDF) 11 Page - Analog Devices |
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11 / 12 page REV. A OP15/OP17 –11– TEST CIRCUITS 100k 7 6 2 3 1 5 4 NOTE:VOS CAN BE TRIMMED WITH POTENTIOMETERS RANGING FROM 10k TO 1M . FOR MOST UNITS TCVOS WILL BE MINIMIZED WHEN VOS IS ADJUSTED WITH A 100k POTENTIOMETER V+ Figure 3. Input Offset Voltage Nulling 100pF 7 2 3 OP15 5k 0.1% 2k 0.1% 2k 0.1% 4 6 +15V 0V 10V –15V SUMMING NODE 5k 0.1% VOUT 2N4416 3k AV = –1 +15V 2k SCOPE 2N4416 Figure 4. OP15 Settling Time Test Circuit 7 2 3 OP17 1k 0.1% 400 0.1% 2k 0.1% 4 6 +15V 0V 10V –15V SUMMING NODE 5k 0.1% VOUT 2N4416 3k AV = –1 +15V 2k SCOPE 2N4416 100pF Figure 6. OP17 Settling Time Test Circuit APPLICATION INFORMATION Dynamic Operating Considerations As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance for the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to ac ground set the frequency of this pole. In many instances the frequency of this pole is much greater than the expected, 3 dB frequency of the close-loop gain, and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approxi- mately six times the expected 3 dB frequency, a lead capacitor should be placed from the output to the negative input of the op amp. The value of the added capacitor should be such that the RC time-constant of this capacitor and the resistance it parallels is greater than, or equal to, the original feedback pole time is constant. 5 MSB 6 7 8 9 10 11 12 LSB B1 B2 B3 B4 B5 B6 B7 B8 DIGITAL INPUTS DAC08E +10V VREF+ VREF– 13 16 1 +15V –15V C1 0.1 F 3 V+ V– CC VLC IO IO 4 2 2 3 +15V –15V OP15F 7 4 6 VO = 0V TO 10V C2 30pF R2 5k R1 10k RREF 5k 14 15 Figure 5. Current-to-Voltage Amplifier Output |
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