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OP15AJMDA bảng dữ liệu(PDF) 1 Page - Analog Devices |
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OP15AJMDA bảng dữ liệu(HTML) 1 Page - Analog Devices |
1 / 12 page REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a OP15/OP17 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 Precision JFET-Input Operational Amplifiers OUTPUT *R7, R8 ARE ELECTRONICALLY ADJUSTED ON CHIP FOR MINIMUM OFFSET VOLTAGE. J3 C1 7.4pF J4 J1 J2 Q5 J5 Q6 Q7 R3 Q8 NONINVERTING INPUT R1 –INV INPUT V+ V– R8* J8 R7* NULL NULL J11 Q12 Q11 R4 Q1 Q2 R3 Q3 Q4 R5 3.6k Q16 Q13 Q16 J6 Q9 R2 C2 R6 3.6k Q15 Q14 Q19 Q17 Q10 J9 Q21 Q20 R13 Q24 Q22 J10 Q23 Q25 R11 Figure 1. Simplified Schematic FEATURES Significant Performance Advantages over LF155 and LF157 Devices Low Input Offset Voltages: 500 V Max Low Input Offset Voltage Drift: 2.0 V/ C Minimum Slew Rate Guaranteed on All Models Temperature-Compensated Input Bias Currents Bias Current Specified Warmed-Up Over Temperature Internal Compensation Low Input Noise Current: 0.01 pA/ ÷÷÷÷÷Hz High Common-Mode Rejection Ratio: 100 dB Models with MIL-STD 883 Processing Available OP15 156 Speed with 155 Dissipation: 80 mW Typ Wide Bandwidth: 6 MHz High Slew Rate: 13 V/ s Fast Settling to ±0.1%: 1,200 ns OP17 Highest Slew Rate: 60 V/ s Fastest Settling to ±0.1%: 600 ns Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz Guaranteed Input Bias Current @ 125 C GENERAL DESCRIPTION The ADI-JFET input series of devices offer clear advantages over industry-generic devices and are superior in both cost and perfor- mance to many dielectrically-isolated and hybrid op amps. All devices offer offset voltages as low as 0.5 mV with TCVOS guaranteed to 5 mV/∞C. A unique input bias cancellation circuit reduces the IB by a factor 10 over conventional designs. In addition ADI specifies IB and IOS with the devices warmed up and operating at 25 ∞C ambient. These devices were designed to provide real precision performance along with high speed. Although they can be nulled, the design objective was to provide low offset-voltage without nulling. Systems generally become more cost effective as the number of trim circuits is decreased. ADI achieves this performance by use of an improved bipolar compatible JFET process coupled with on chip, zener-zap offset trimming. The OP15 provides an excellent combinations of high speed and low input offset voltage. In addition, the OP15 offers the speed of the 156A op amp with the power dissipation of a 155A. The combination of a low input offset voltage of 500 mV, slew rate of 13 V/ ms, and settling time of 1,200 ns to 0.1% makes the OP15 an op amp of both precision and speed. The additional features of low supply current coupled with an input bias current makes the OP15 ideal for a wide range of applications. The OP17 has a slew rate of 60 V/ ms and is the best choice for applications requiring high closed-loop gain with high speed. See OP42 datasheet for unity gain applications and the OP215 datasheet for a dual configuration of the OP15. |
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