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AD9879 bảng dữ liệu(PDF) 10 Page - Analog Devices

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REV. 0
–10–
AD9879
REGISTER BIT DEFINITIONS
Register 00 — Initialization
Bits 0 to 4: OSCIN Multiplier
This register field is used to program the on-chip multiplier
(PLL) that generates the chip’s high frequency system clock
fSYSCLK. The value of M will depend on the ADC clocking mode
selected as shown in the table below.
Table II.
ADC Clock Select
M
1, fOSCIN
8
0, fMCLK (PLL Derived)
16
When using the AD9879 in systems where the Tx path and Rx
path do not operate simultaneously, the value of M can be pro-
grammed from 1 to 31. The maximum fSYSCLK rate of 236 MHz
must be observed, whatever value is chosen for M. When M is
set to 1, the internal PLL is disabled and all internal clocks are
derived directly from OSCIN.
Bit 5: Reset
Writing a 1 to this bit resets the registers to their default values
and restarts the chip. The Reset bit always reads back 0. The
bits in Register 0 are not affected by this software reset. How-
ever, a low level at the
RESET pin would force all registers,
including all bits in Register 0, to their default state.
Bit 6: SPI Bytes LSB First
Active high indicates SPI serial port access of instruction byte
and data registers is least significant bit (LSB) first. Default low
indicates most significant bit (MSB) first format.
Bit 7: SDIO Bidirectional
Active high configures the serial port as a three signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates the serial port uses four signals with SDIO config-
ured as an input and SDO configured as an output.
Register 01 — Clock Configuration
Bits 0 to 5: MCLK/REFCLK Ratio
This bit field defines, R, the ratio between the auxiliary clock
output, REFCLK and MCLK. R can be any integer number
between 2 and 63. At default zero (R = 0), REFCLK provides a
buffered version of the OSCIN clock signal.
Bit 7: PLL Lock Detect
When this bit is set low, the REFCLK pin functions in its default
mode, and provides an output clock with frequency fMCLK/R as
described above.
If this bit is set to 1, the REFCLK pin is configured to indicate
whether the PLL is locked to fOSCIN. In this mode, the REFCLK
pin should be low-pass filtered with an RC filter of 1.0 k
W and
0.1
mF. A high output on REFCLK indicates that the PLL has
achieved lock with fOSCIN.
Register 02 — POWER-DOWN
Sections of the chip that are not used can be powered down
when the corresponding bits are set high. This register has a
default value of 0x00; all sections active.
Bit 0: Power-Down IQ ADC
Active high powers down the IQ ADC.
Bit 1: Power-Down IQ and IF10 ADC Reference
Active high powers down the IQ and IF10 ADC reference.
Bit 2: Power-Down IF10 ADC
Active high powers down the IF10 ADC.
Bit 3: Power-Down IF12 ADC Reference
Active high powers down the 12-bit ADC reference.
Bit 4: Power-Down IF12 ADC
Active high powers down the IF12 ADC.
Bit 5: Power-Down Digital TX
Active high powers down the digital transmit section of the chip,
similar to the function of the PWRDN Pin.
Bit 6: Power-Down DAC TX
Active high powers down the DAC.
Bit 7: Power-Down PLL
Active high powers down the OSCIN multiplier.
Registers 03 and 04 — Sigma-Delta and Flag Control
The sigma-delta control word is 12 bits wide and split in MSB bits
[11:4] and LSB bits [3:0]. Changes to the sigma-delta control
words take effect immediately for every MSB or LSB register
write. Sigma-delta output control words have a default value of
“0.” The control words are in straight binary format with 0x000
corresponding to the bottom of the scale and 0xFFF correspond-
ing to the top of the scale. See Figure 6 for details.
If the Flag 0 Enable (Register 3, Bit 0) is set high, the - _OUT
pin will maintain a fixed logic level determined directly by the
MSB of the sigma-delta control word.
The FLAG1 pin assumes the logic level programmed into the
FLAG1 bit (Register 3, Bit 1).
Register 07 —VIDEO INPUT CONFIGURATION
Bits 0-6: Clamp Level Control Value
The 7-bit clamp level control value is used to set an offset to the
automatic clamp level control loop. The actual ADC output will
have a clamp level offset equal to 16 times the clamp level control
value as shown:
Clamp Level Offset
Clamp Level Control Value
()16
The default value for the clamp level control value is 0x20. This
results in an ADC output clamp level offset of 512 LSBs. The
valid programming range for the clamp level control value is
from 0x16 to 0x127.
Register 08 — ADC CLOCK CONFIGURATION
Bit 0: Send 10-Bit ADC Data Only
When this bit is set high, the device enters a Nonmultiplexed
mode and only the data from the 10-bit ADC will be sent to the
IF [11:0] digital output port.
Bit 1: Send 12-Bit ADC Data Only
When this bit is set high, the device enters a Nonmultiplexed
mode and only data from the 12-bit ADC will be sent to the IF
[11:0] digital output port.
Bit 3: Enable 7-Bits, IQ ADC
When this bit is active the IQ ADC is put into 7-bit mode. In
this mode, the full-scale input range is 2 Vppd. When this bit is
set inactive, the IQ ADC is put into 6-bit mode and the full-
scale input voltage range is 1 Vppd.
Bit 4: Power-Down RXSYNC and IQ ADC Clocks
Setting this bit to 1 powers down the IQ ADC’s sampling clock
and stops the RXSYNC output pin. It can be used for additional
power saving on top of the power-down selections in Register 2.


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