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74LVX373MTC bảng dữ liệu(PDF) 2 Page - National Semiconductor (TI) |
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2 / 8 page Functional Description The LVX373 contains eight D-type latches with TRI-STATE standard outputs When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this con- dition the latches are transparent ie a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW tran- sition of LE The TRI-STATE standard outputs are con- trolled by the Output Enable (OE) input When OE is LOW the standard outputs are in the 2-state mode When OE is HIGH the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches Truth Table Inputs Outputs LE OE Dn On XH X Z HL L L HL H H LL X O0 H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance X e Immaterial O0 e Previous O0 before HIGH to Low transition of Latch Enable Logic Diagram TLF11613 – 3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays http www nationalcom 2 |
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