Philips Semiconductors

Product data

74ABT5074

Synchronizing dual D-type flip-flop

with metastable immune characteristics

2

2002 Dec 17

FEATURES

applications

and 200 V per Machine Model

DESCRIPTION

The 74ABT5074 is a dual positive edge-triggered D-type flip-flop

featuring individual data, clock, set and reset inputs; also true and

complementary outputs.

Set (SDn) and reset (RDn) are asynchronous active-LOW inputs

and operate independently of the clock (CPn) input. Data must be

stable just one set-up time prior to the LOW-to-HIGH transition of

the clock for guaranteed propagation delays.

Clock triggering occurs at a voltage level and is not directly related

to the transition time of the positive-going pulse. Following the hold

time interval, data at the Dn input may be changed without affecting

the levels of the output.

The 74ABT5074 is designed so that the outputs can never display a

metastable state due to set-up and hold time violations. If set-up

time and hold time are violated the propagation delays may be

extended beyond the specifications, but the outputs will not glitch or

display a metastable state. Typical metastability parameters for the

74ABT5074 are:

where

τ represents a function of the rate at which a latch in a

function of the measurement of the propensity of a latch to enter a

metastable state.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay

CPn to Qn or Qn

2.8

2.4

ns

Input capacitance

3

pF

Total supply current

2

µA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

PART NUMBER

DWG NUMBER

14-Pin plastic SO

–40

°C to +85 °C

74ABT5074D

SOT108-1

14-Pin Plastic SSOP Type II

–40

°C to +85 °C

74ABT5074DB

SOT337-1

14-Pin Plastic TSSOP Type I

–40

°C to +85 °C

74ABT5074PW

SOT402-1

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

SD1

Q1

Q1

CP1

RD1

D1

RD0

D0

Q0

CP0

SD0

Q0

SA00001

PIN DESCRIPTION

PIN

SYMBOL

NAME AND FUNCTION

2, 12

D0, D1

Data inputs

3, 11

CP0, CP1

Clock inputs (active rising edge)

4, 10

SD0, SD1

Set inputs (active-LOW)

1, 13

RD0, RD1

Reset inputs (active-LOW)

5, 9

Q0, Q1

Data outputs (active-LOW), non-inverting

6, 8

Q0, Q1

Data outputs (active-LOW), inverting

7

GND

Ground (0 V)

14

Positive supply voltage