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STLC2500A
Electrical characteristics
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2.3
I/O specifications
The I/Os comply with the EIA/JEDEC standard JESD8-B.
Note:
X is the source/sink current under worst-case conditions according to the drive capabilities
(see Chapter 6)
2.4
Clock specifications
The STLC2500A supports, on the same input pin, the system clock both as a sine wave
clock and as a digital clock (see
Table 14 for selection). The system clock section is powered
by VDD_CLD (G08 and H09). The voltage range for VDD_CLD is the same as for
VDD_IO_A.
Table 3.
DC input specification (all digital I/Os except system clock)
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIL
Low Level input voltage
0.35 *
VDD_IO_x
V
VIH
High Level input voltage
0.65 *
VDD_IO_x
V
Vhyst
Schmitt trigger hysteresis
0.4
0.5
0.6
V
Table 4.
DC output specification
Symbol
Parameter
Min.
Typ.
Max.
Unit
VOL
Low Level output voltage
Id = X mA
0.15
V
VOH
High Level output voltage
Id = X mA
VDD_IO_x
- 0.15
Table 5.
System clock supported frequencies
Symbol
Parameter
Values
Unit
FIN
Clock input frequency list
13, 26, 19.2, 38.4
MHz
Table 6.
System clock overall specifications
Symbol
Parameter
Min.
Typ.
Max.
Unit
FINTOL
Tolerance on input frequency
-20
20
ppm


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