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74ABTH16823ADGG bảng dữ liệu(PDF) 8 Page - NXP Semiconductors |
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74ABTH16823ADGG bảng dữ liệu(HTML) 8 Page - NXP Semiconductors |
8 / 12 page Philips Semiconductors Product specification 74ABT16823A 74ABTH16823A 18-bit bus-interface D-type flip-flop with reset and enable (3-State) 1998 Feb 27 8 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VM SH00017 nCP nQx VM tw(H) tPHL VM tPLH 1/fMAX tw(L) VM 3.0V or VCC whichever is less 0V 0V VOH Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM nMR VM nQx tw(L) VM tPHL VM tREC nCP SH00018 3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less 0V 0V VOH Waveform 2. Master Reset Pulse WIdth, Master Reset to Output Delay and Master Reset to Clock Recovery Time th(H) ts(H) nCP VM VM VM VM VM VM th(L) ts(L) nDx, nCE SH00019 3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less 0V Waveform 3. Data Setup and Hold Times VOH–0.3V VM VM VM nQx tPZH tPHZ nOE 0V VOH SH00020 3.0V or VCC whichever is less 0V Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level nOE tPZL tPLZ VOL +0.3V nQx SH00021 VM VM VM VOL 3.0V or VCC whichever is less 0V 3.0V or VCC whichever is less Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level |
Số phần tương tự - 74ABTH16823ADGG |
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