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ADC12DL080EVAL bảng dữ liệu(PDF) 7 Page - National Semiconductor (TI) |
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ADC12DL080EVAL bảng dữ liệu(HTML) 7 Page - National Semiconductor (TI) |
7 / 24 page Converter Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) DYNAMIC CONVERTER CHARACTERISTICS FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 600 MHz SNR Signal-to-Noise Ratio (Note 16) f IN = 40 MHz, VIN = −1 dBFS 69.3 67 dBFS (min) f IN = 200 MHz, VIN = −1 dBFS 67 dBFS SINAD Signal-to-Noise and Distortion (Note 16) f IN = 40 MHz, VIN = −1 dBFS 69 66.5 dBFS (min) f IN = 200 MHz, VIN = −1 dBFS 66.5 dBFS ENOB Effective Number of Bits (Note 16) f IN = 40 MHz, VIN = −1 dBFS 11 10.75 Bits (min) f IN = 200 MHz, VIN = −1 dBFS 10.75 Bits THD Total Harmonic Distortion f IN = 40 MHz, VIN = −1 dBFS −80 -71 dBc (min) f IN = 200 MHz, VIN = −1 dBFS −76.8 dBc H2 Second Harmonic Distortion f IN = 40 MHz, VIN = −1 dBFS −85 -73 dBc (min) f IN = 200 MHz, VIN = −1 dBFS −84 dBc H3 Third Harmonic Distortion f IN = 40 MHz, VIN = −1 dBFS −82 -74 dBc (min) f IN = 200 MHz, VIN = −1 dBFS −81 dBc SFDR Spurious Free Dynamic Range f IN = 40 MHz, VIN = −1 dBFS 82 73 dBc (min) f IN = 200 MHz, VIN = −1 dBFS 81 dBc IMD Intermodulation Distortion f IN = 19.6 MHz and 20.2 MHz, each = −6.5 dBFS −70 dBFS INTER-CHANNEL CHARACTERISTICS Channel — Channel Offset Match ±0.3 %FS Channel — Channel Gain Match ±0.4 %FS Crosstalk 10 MHz Tested, Channel; 20 MHz Other Channel 90 dBc DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) DIGITAL INPUT CHARACTERISTICS V IN(1) Logical “1” Input Voltage V D = 3.6V 2.0 V (min) V IN(0) Logical “0” Input Voltage V D = 3.0V 1.0 V (max) I IN(1) Logical “1” Input Current V IN = 3.3V 10 µA I IN(0) Logical “0” Input Current V IN = 0V −10 µA C IN Digital Input Capacitance 5 pF DIGITAL OUTPUT CHARACTERISTICS V OUT(1) Logical “1” Output Voltage I OUT = −0.5 mA V DR = 2.5V 2.3 V (min) V DR =3V 2.7 V (min) V OUT(0) Logical “0” Output Voltage I OUT = 1.6 mA, VDR =3V 0.4 V (max) I OZ TRI-STATE® Output Current V OUT = 2.5V or 3.3V 100 nA V OUT = 0V −100 nA +I SC Output Short Circuit Source Current V OUT = 0V −20 mA −I SC Output Short Circuit Sink Current V OUT =VDR 20 mA C OUT Digital Output Capacitance 5 pF www.national.com 7 |
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