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ADM1068 bảng dữ liệu(PDF) 5 Page - Analog Devices

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Preliminary Technical Data
ADM1068
Rev. PrB | Page 5 of 28
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
500
kΩ
VOH
11
12.5
14
V
IOH = 0
10.5
12
13.5
V
IOH = 1 µA
IOUTAVG
20
µA
2 V < VOH < 7 V
Standard (Digital Output) Mode (PDO1–8)
VOH
2.4
V
VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
4.5
V
VPU to Vpn = 6.0 V, IOH = 0 mA
VPU − 0.3
V
VPU ≤ 2.7 V, IOH = 0.5 mA
VOL
0
0.50
V
IOL = 20 mA
IOL2
20
mA
Maximum sink current per PDO pin
ISINK2
60
mA
Maximum total sink for all PDOs
RPULL-UP
20
kΩ
Internal pull-up
ISOURCE (VPn)2
2
mA
Current load on any VPn pull- ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
Three-State Output Leakage Current
10
µA
VPDO = 14.4 V
Oscillator Frequency
90
100
110
kHz
All on-chip time delays derived from this clock
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, VIH
2.0
V
Maximum VIN = 5.5 V
Input Low Voltage, VIL
0.8
V
Maximum VIN = 5.5 V
Input High Current, IIH
−1
µA
VIN = 5.5 V
Input Low Current, IIL
1
µA
VIN = 0
Input Capacitance
5
pF
Programmable Pull-Down Current,
IPULL-DOWN
20
µA
VDDCAP = 4.75, TA = 25°C, if known logic state is
required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL2
0.4
V
IOUT = −3.0 mA
SERIAL BUS TIMING
Clock Frequency, fSCLK
400
kHz
Bus Free Time, tBUF
4.7
µs
Start Setup Time, tSU;STA
4.7
µs
Start Hold Time, tHD;STA
4
µs
SCL Low Time, tLOW
4.7
µs
SCL High Time, tHIGH
4
µs
SCL, SDA Rise Time, tr
1000
µs
SCL, SDA Fall Time, tf
300
µs
Data Setup Time, tSU;DAT
250
ns
Data Hold Time, tHD;DAT
5
ns
Input Low Current, IIL
1
µA
VIN = 0
SEQUENCING ENGINE TIMING
State Change Time
10
µs
1 At least one of the VH, VP1–3 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested, but is supported by characterization data at initial product release.


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