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STK22C48
December 2002
5
Document Control # ML0004 rev 0.0
HARDWARE MODE SELECTION
Note m: HSB STORE operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note n: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
HARDWARE STORE CYCLE
(VCC = 5.0V ± 10%)e
Note o: E and G low for output behavior.
Note p: E and G low and W high for output behavior.
Note q: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
E
W
HSB
A12 - A0 (hex)
MODE
I/O
POWER
NOTES
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
n
L
L
H
X
Write SRAM
Input Data
Active
X
X
L
X
Nonvolatile
STORE
Output High Z
lCC
2
m
NO.
SYMBOLS
PARAMETER
STK22C48
UNITS NOTES
Standard
Alternate
MIN
MAX
22
tSTORE
tHLHZ
STORE Cycle Duration
10
ms
i, o
23
tDELAY
tHLQZ
Time Allowed to Complete SRAM Cycle
1
µsi, p
24
tRECOVER
tHHQX
Hardware STORE High to Inhibit Off
700
ns
o, q
25
tHLHX
Hardware STORE Pulse Width
15
ns
26
tHLBL
Hardware STORE Low to Store Busy
300
ns
DATA VALID
HSB (IN)
DATA VALID
25
tHLHX
23
tDELAY
22
tSTORE
24
tRECOVER
HSB (OUT)
HIGH IMPEDANCE
26
tHLBL
HIGH IMPEDANCE
DQ (DATA OUT)
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