công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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LM73CIMK bảng dữ liệu(PDF) 5 Page - National Semiconductor (TI) |
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LM73CIMK bảng dữ liệu(HTML) 5 Page - National Semiconductor (TI) |
5 / 18 page Logic Electrical Characteristics DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for V DD = 2.7V to 5.5V. Boldface limits apply for TA =TJ =TMIN to TMAX; all other limits T A =TJ = +25˚C, unless otherwise noted. TA is the ambient temperature. TJ is the junction temperature. Symbol Parameter Conditions Typical Limits Units (Note 6) (Note 7) (Limit) SMBDAT, SMBCLK INPUTS V IH Logical “1” Input Voltage 0.7*V DD V (min) V IL Logical “0” Input Voltage 0.3*V DD V (max) V IN;HYST SMBDAT and SMBCLK Digital Input Hysteresis 0.07*V DD V I IH Logical “1” Input Current V IN =VDD 0.01 2 µA (max) I IL Logical “0” Input Current V IN = 0 V –0.01 –2 µA (max) C IN Input Capacitance 5 pF SMBDAT, ALERT OUTPUTS I OH High Level Output Current V OH =VDD 0.01 2 µA (max) V OL SMBus Low Level Output Voltage I OL =3mA 0.4 V (max) ADDRESS INPUT V IH;ADDRESS Address Pin High Input Voltage V DD minus 0.100 V (min) V IL;ADDRESS Address Pin Low Input Voltage 0.100 V (max) I IH; ADDRESS Address Pin High Input Current V IN =VDD 0.01 2 µA (max) I IL;ADDRESS Address Pin Low Input Current V IN = 0 V –0.01 –2 µA (max) SMBus DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for V DD = +2.7 V to +5.5 V, CL (load capacitance) on output lines = 400 pF. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C, unless otherwise noted. Symbol Parameter Conditions Typical Limits Units (Note 6) (Note 7) (Limit) f SMB SMBus Clock Frequency 400 100 kHz (max) Hz (min) t LOW SMBus Clock Low Time 300 ns (min) t HIGH SMBus Clock High Time 300 ns (min) t F;SMBO Output Fall Time (Note 10) C L = 400 pF I PULL-UP ≤ 3mA 250 ns (max) t TIMEOUT SMBDAT and SMBCLK Time Low for Reset of Serial Interface (Note 11) 15 45 ms (min) ms (max) t SU;DAT Data In Setup Time to SMBCLK High 100 ns (min) t HD;DATI Data Hold Time: Data In Stable after SMBCLK Low 0 ns (min) t HD;DATO Data Hold Time: Data Out Stable after SMBCLK Low 30 ns (min) t HD;STA Start Condition SMBDAT Low to SMBCLK Low (Start condition hold before the first clock falling edge) 60 ns (min) t SU;STO Stop Condition SMBCLK High to SMBDAT Low (Stop Condition Setup) 50 ns (min) t SU;STA SMBus Repeated Start-Condition Setup Time, SMBCLK High to SMBDAT Low 50 ns (min) t BUF SMBus Free Time Between Stop and Start Conditions 1.2 µs (min) t POR Power-On Reset Time (Note 12) 1 ms (max) www.national.com 5 |
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