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LM26001 bảng dữ liệu(PDF) 8 Page - National Semiconductor (TI) |
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LM26001 bảng dữ liệu(HTML) 8 Page - National Semiconductor (TI) |
8 / 16 page Operation Description (Continued) the reset threshold, at which point switching resumes. This 1% FB window limits the corresponding output ripple to approximately 1% of nominal output voltage. The sleep cycle will repeat until load current is increased. Figure 2 shows typical switching and output voltage waveforms in sleep mode. In sleep mode, quiescent current is reduced to less than 40 µA when not switching. The DC sleep mode threshold can be calculated according to the equation below: Where Imin=Ilim/16 (2.5A/16 typically) and D=duty cycle, defined as (Vout+Vdiode)/Vin. When load current increases above this limit, the LM26001 is forced back into PWM operation. The sleep mode thresh- old varies with frequency, inductance, and duty cycle as shown in Figure 3. FPWM Pulling the FPWM pin high disables sleep mode and forces the LM26001 to always operate in PWM mode. Light load efficiency is reduced in PWM mode, but switching frequency remains stable. The FPWM pin can be connected to the VDD pin to pull it high. In FPWM mode, under light load conditions, the regulator operates in discontinuous conduc- tion mode (DCM) . In discontinuous conduction mode, cur- rent through the inductor starts at zero and ramps up to its peak, then ramps down to zero again. Until the next cycle, the inductor current remains at zero. At nominal load cur- rents, in FPWM mode, the device operates in continuous conduction mode, where positive current always flows in the inductor. Typical discontinuous operation waveforms are shown below. At very light load, in FPWM mode, the LM26001 may enter sleep mode. This is to prevent an over-voltage condition from occurring. However, the FPWM sleep threshold is much lower than in normal operation. ENABLE The LM26001 provides a shutdown function via the EN pin to disable the device when the output voltage does not need to be maintained. EN is an analog level input with typically 164 mV of hysteresis. The device is active when the EN pin is above 1.1V (typical) and in shutdown mode when EN is below this threshold. When EN goes high, the internal VDD regulator turns on and charges the VDD capacitor. When VDD reaches 3.9V (typical), the soft-start pin begins to source current. In shutdown mode, the VDD regulator shuts down and total quiescent current is reduced to 10 µA (typi- cal). Because the EN pin sources 4.5 µA (typical) of pull-up current, this pin can be left open for always-on operation. When open, EN will be pulled up to VIN. If EN is connected to VIN, it must be connected through a 10 k Ω resistor to limit noise spikes. EN can also be driven externally with a maximum voltage of 38V or VIN + 15V, whichever is lower. SOFT-START The soft-start feature provides a controlled output voltage ramp up at startup. This reduces inrush current and elimi- nates output overshoot at turn-on. The soft-start pin, SS, must be connected to GND through a capacitor. At power- 20179420 FIGURE 2. Sleep Mode Waveforms 25mA Load, Vin = 12V 20179422 FIGURE 3. Sleep Mode Threshold vs Vin Vout = 3.3V 20179423 FIGURE 4. Discontinuous Mode Waveforms 75mA Load, Vin = 12V www.national.com 8 |
Số phần tương tự - LM26001 |
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Mô tả tương tự - LM26001 |
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