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GS1503-CFZ bảng dữ liệu(PDF) 10 Page - Gennum Corporation |
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GS1503-CFZ bảng dữ liệu(HTML) 10 Page - Gennum Corporation |
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10 / 83 page  15879 - 4 10 of 83 22 OPERATE O Audio processing indicator. When HIGH, audio data is being multiplexed or demultiplexed. 23 CRC_ERROR O CRC error indicator. Will be set HIGH when a CRC error is detected in the incoming video data stream. 24 PKTENO O Arbitrary data packet timing signal. Valid in Multiplex Mode only. Will be HIGH when arbitrary data packets can be input to the device. This signal is only valid when multiplexing arbitrary data packets via the PKT[7:0] bus. See Figure 30 for timing. 25 PKTEN I/O Arbitrary data packet enable. In Multiplex Mode, PKTEN is an input and must be set HIGH two VCLK cycles after the PKTENO signal goes HIGH. Arbitrary packet data is input to the device two VCLK cycles after PKTEN is set HIGH. In Demultiplex Mode, PKTEN is an output and is set HIGH two VCLK cycles before the device outputs arbitrary packet data. See Figures 30 and 42. 26, 28, 29, 30, 32, 33, 34, 35 PKT[7:0] I/O Arbitrary data I/O bus. PKT[7] is the MSB and PKT[0] is the LSB. In Multiplex Mode, the user must input the arbitrary data packet words starting from the data identification (DID) to the last user data word (UDW) according to SMPTE 291M. The GS1503 internally converts the data to 10 bits by generating the parity bit (bit 8) and inversion bit (bit 9). The checksum (CS) word is also generated internally. In Demultiplex Mode, the GS9023 outputs the arbitrary data packet words starting from the DID to the last UDW. See Figures 30 and 42. 38 SCRBYPASS I Scrambler bypass. When set LOW, the output video stream is scrambled according to SMPTE 292M and NRZ(I) encoded. When set HIGH, the scrambler and NRZ(I) encoder are bypassed. 39, 40, 41, 42 RSV - Connect to ground. 43 EXTH I/O Horizontal sync signal. The GS1503 outputs a horizontal sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a horizontal sync signal can be input to the device for TRS and line number insertion. 44 EXTF I/O Field sync signal. The GS1503 outputs a field sync signal derived from the incoming TRS. In Multiplex Mode, with EXT_SEL set HIGH in the Host Interface, a field sync signal can be input to the device for TRS and line number insertion. For progressive formats, a signal with a high to low transition at the position of line one must be provided. See Figures 14 and 15. 45 VIDEO_DET O Video input signal detection. Indicates that the device has detected a valid video input stream. NOTE: When EXT_SEL is set HIGH in the Host Interface, VIDEO_DET will indicate when valid EXTH and EXTF signals have been detected. 71, 70, 69, 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47, 46 VOUT[19:0] O Parallel digital video signal output. VOUT[19] is the MSB and VOUT[0] is the LSB. 74 WCOUTA O 48kHz word clock for channels 1 to 4. Valid only when operating in Demultiplex Mode. 75 WCOUTB O 48kHz word clock for channels 5 to 8. Valid only when operating in Demultiplex Mode. 76 AOUT1/2 O Audio signal output for channels 1 and 2. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 77 AOUT3/4 O Audio signal output for channels 3 and 4. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. 78 AOUT5/6 O Audio signal output for channels 5 and 6. The AES/EBU digital audio output is bi-phase mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded. PIN DESCRIPTIONS (Continued) NUMBER SYMBOL TYPE DESCRIPTION |
Số phần tương tự - GS1503-CFZ |
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Mô tả tương tự - GS1503-CFZ |
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