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DAC8831IBD bảng dữ liệu(PDF) 7 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
tên linh kiện DAC8831IBD
Giải thích chi tiết về linh kiện  16-Bit, Ultra-Low Power, Voltage-Output Digital-to-Analog Converters
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DAC8831IBD bảng dữ liệu(HTML) 7 Page - Burr-Brown (TI)

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TIMING CHARACTERISTICS: V
DD = +5 V
(1) (2)
TIMING CHARACTERISTICS: V
DD = +3 V
(1) (2)
DAC8830
DAC8831
SLAS449C – FEBRUARY 2005 – REVISED NOVEMBER 2006
At –40
°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
µs
(1)
Assured by design. Not production tested.
(2)
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
At –40
°C to +85°C, unless otherwise noted.
PARAMETER
MIN
MAX
UNIT
tsck
SCLK period
20
ns
twsck
SCLK high or low time
10
ns
tDelay
Delay from SCLK high to CS low
10
ns
tLead
CS enable lead time
10
ns
tLag
CS enable lag time
10
ns
tDSCLK
Delay from CS high to SCLK high
10
ns
ttd
CS high between active period
30
ns
tsu
Data setup time (input)
10
ns
tho
Data hold time (input)
0
ns
tWLDAC
LDAC width
30
ns
tDLDAC
Delay from CS high to LDAC low
30
ns
VDD high to CS low (power-up delay)
10
µs
(1)
Assured by design. Not production tested.
(2)
Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
7
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Số phần tương tự - DAC8831IBD

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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Mô tả tương tự - DAC8831IBD

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