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AD1941 bảng dữ liệu(PDF) 11 Page - Analog Devices

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AD1941 bảng dữ liệu(HTML) 11 Page - Analog Devices

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Preliminary Technical Data
AD1941
Rev. PrE | Page 11 of 32
PIN FUNCTIONS
Table 10 shows the AD1941’s pin numbers, names, and
functions. Input pins have a logic threshold compatible with
TTL input levels and may be used in systems with 3.3 V or
5 V logic.
SDATA_IN0
SDATA_IN1
SDATA_IN2/TDM_IN1
SDATA_IN3/TDM_IN0
Serial Data/TDM Inputs. The serial format is selected by writing
to Bits 2:0 of the serial input port control register. SDATA_IN2
and SDATA_IN3 are dual-function pins that can be set to a
variety of standard 2-channel formats or to TDM mode. Two of
these four pins (SDATA_IN2 and SDATA_IN3) can be used as
TDM inputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_O0 only). In dual-wire 8-channel
mode, Channels 0-7 will be input on SDATA_IN3 and
Channels 8-15 on SDATA_IN2. In single-wire 16-channel
mode, Channels 0-15 will be input on SDATA_IN2. See the
Serial Data Input/Output Ports section for further explanation.
LRCLK_IN
BCLK_IN
Left/Right and Bit Clocks for Timing the Input Data. These
input clocks are associated with the SDATA_IN0-3 signals. The
input port is always in a slave configuration. These pins also
function as frame sync and bit clock for the input TDM stream.
SDATA_OUT0/TDM_O0
SDATA_OUT1
SDATA_OUT2,
SDATA_OUT3
SDATA_OUT4/TDM_O1
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7/DCSOUT
Serial Data/TDM/Data Capture Outputs. These pins are used
for serial digital outputs. For non-TDM systems, these eight
pins can output 16 channels of digital audio, using a variety of
standard two-channel formats. They are grouped into two
groups of four pins (0-3 and 4-7); each group can be indepen-
dently set to any of the available serial modes, allowing the
AD1941 to simultaneously communicate with two external
devices with different serial formats. Two of these eight pins
(SDATA_OUT0 and SDATA_OUT4) can be used as TDM
outputs in either dual-wire 8-channel mode or single-wire
16-channel mode (TDM_OUT0 only). In dual-wire 8-channel
mode, Channels 0-7 will be output on SDATA_OUT0 and
Channels 8-15 on SDATA_OUT4. See the Serial Data
Input/Output Ports section for further explanation.
SDATA_OUT7 can also be used as a data capture output, as
described in the Data Capture Registers section.
LRCLK_OUT0
BCLK_OUT0
Output Clocks. This clock pair is used for outputs
SDATA_OUT0–3. In slave mode, these clocks are inputs
to the AD1941. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
LRCLK_OUT1
BCLK_OUT1
Output Clocks. This clock pair is used for outputs
SDATA_OUT4–7. In slave mode, these clocks are inputs
to the AD1941. On power-up, these pins are set to slave
mode to avoid conflicts with external master-mode devices.
MCLK
Master Clock Input. The AD1941 uses a PLL to generate the
appropriate internal clock for the DSP core. An in-depth
description of using the PLL is found in the Setting Master
Clock/PLL Mode section.
PLL_CTRL0
PLL_CTRL1
PLL_CTRL2
PLL Mode Control Pins. The functionality of these pins is
described in the Setting Master Clock/PLL Mode section.
SCL
I2C Clock. This pin is always an input because the AD1941
cannot act as a master on the I2C bus. The line connected to this
pin should have a 2 kΩ pull-up resistor on it.
SDA
I2C Serial Data. The data line is bidirectional. The line
connected to this pin should have a 2 kΩ pull-up resistor on it.
I2C_FILT_ENB
I2C Spike Filter Enable/Disable. This enables (active low) the I2C
spike filter, which is used to prevent noise or glitches on the I2C
bus, from improperly affecting the AD1941.
ADR_SEL
Address Select. This pin selects the address for the AD1941’s
communication with the control port. This allows two AD1941s
to be used with a single CLATCH signal.
RESETB
Active-Low Reset Signal. After RESETB goes high, the AD1941
goes through an initialization sequence where the program and
parameter RAMs are initialized with the contents of the on-
board boot ROMs. All registers are set to 0, and the data RAMs
are also set to 0. The initialization is complete after
8,192 internal MCLK cycles (referenced to the rising edge of
RESETB), which corresponds to 1,366 external MCLK cycles if
the part is in 256 × fS mode. New values should not be written to
the control port until the initialization is complete.


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