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Transmitter and Receiver Power-Up/Power-Down Operation Truth Table

The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table

shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin.

H

HIGH Logic Level

L

LOW Logic Level

P

Last Valid State

X

Don’t Care

Z

High-Impedance

Note 3: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a

known low frequency and stay until the clock starts normal operation again.

Note 4: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition)

Note 5: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices.

Note 6: Shorted here means (

(0V to 2.4V) then the input signal is still recognized and the part will respond normally.

Transmitter

PwrDn

Normal

2V

!2V

!2V

!2V

!2V

!2V

TxIn

X

X

Active

Active

TxOut

Z

Z

Active

X

TxCLKIn

X

X

Active

H/L/Z

TxCLKOut

r

Z

Z

Active

(Note 3)

PwrDn

L

L

HHHH

Receiver

PwrDn

RxIn

r

X

X

Active

Active

(Note 4)

(Note 4)

RxOut

Z

L

L/H

P

H

P

RxCLKIn

r

X

X

Active

(Note 4)

Active

(Note 4)

RxCLKOut

Z

(Note 5)

Active

(Note 5)

(Note 5)

(Note 5)

PwrDn

L

L

HHHH

2V

2V

2V

2V

2V

2V