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MC100ES6221AE bảng dữ liệu(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC100ES6221AE bảng dữ liệu(HTML) 4 Page - Freescale Semiconductor, Inc |
4 / 12 page Advanced Clock Drivers Devices 4 Freescale Semiconductor MC100ES6221 Table 5. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to + 110°C) Symbol Characteristics Min Typ Max Unit Condition Clock Input Pair CLK0, CLK0(1) (PECL differential signals) 1. The input pairs CLK0, CLK1 are compatible to differential signaling standards. CLK0 is compatible to LVPECL signals and CLK1 meets both HSTL differential signal specifications. The difference between CLK0 and CLK1 is the differential input threshold voltage (VCMR). VPP Differential Input Voltage(2) 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 0.1 1.3 V Differential operation VCMR Differential Cross Point Voltage(3) 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 1.0 VCC – 0.3 V Differential operation IIN Input Current(1) ±100 µAVIN = VIL or VIN = VIH Clock Input Pair CLK1, CLK1(4) (HSTL differential signals) 4. Clock inputs driven by differential HSTL compatible signals. Only applicable to CLK1, CLK1. VDIF Differential Input Voltage(5) 5. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 0.2 1.4 V VX Differential Cross Point Voltage(6) 6. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 0 0.68 - 0.9 VCC – 0.7 V VIH Input High Voltage VX + 0.1 VX + 0.7 V VIL Input Low Voltage VX – 0.7 VX – 0.1 V IIN Input Current ±100 µAVIN = VX ± 0.2 V Clock Inputs (PECL single ended signals) VIH Input Voltage High VCC – 1.165 VCC – 0.880 V VIL Input Voltage Low VCC – 1.810 VCC – 1.475 V IIN Input Current(7) 7. Inputs have internal pullup/pulldown resistors which affect the input current. ±100 µAVIN = VIL or VIN = VIH PECL Clock Outputs (Q0–19, Q0–19) VOH Output High Voltage VCC – 1.1 VCC – 1.005 VCC – 0.7 V IOH = –30 mA(8) 8. Equivalent to a termination of 50 Ω to VTT. VOL Output Low Voltage VCC – 1.9 VCC – 1.705 VCC – 1.4 V IOL = –5 mA(8) Supply current and VBB IEE(9) 9. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷ Rload + IEE. Maximum Quiescent Supply Current without Output Termination Current 84 160 mA VEE pins VBB Output Reference Voltage (fref < 1.0 GHz)(10) 10. Using VBB to bias unused single-ended inputs is recommended only up to a clock reference frequency of 1 GHz. Above 1 GHz, only differential input signals should be used with the MC100ES6221. VCC – 1.42 VCC – 1.20 V IBB = 0.4 mA |
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Mô tả tương tự - MC100ES6221AE |
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