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MC100ES6220AE bảng dữ liệu(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC100ES6220AE bảng dữ liệu(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 12 page Advanced Clock Drivers Devices 2 Freescale Semiconductor MC100ES6220 Figure 1. MC100ES6220 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) VCC QA0 VBB CLKB VCC Fanout Buffer B Fanout Buffer A VEE VEE QA0 QA1 QA1 QA8 QA8 QA9 QA9 QB0 QB0 QB8 QB8 QB1 QB1 QB9 QB9 CLKB CLKA CLKA VCC QA5 QA5 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0 QB2 QB2 QB3 QB3 QB4 QB4 QB5 QB5 QB6 QB6 QB7 QB7 VCC 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 12 345 67 89 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MC100ES6220 QA4 Table 1. Pin Configuration Pin I/O Type Function CLKA, CLKA Input ECL/PECL Differential reference clock signal input for fanout buffer A CLKB, CLKB Input ECL/PECL Differential reference clock signal input for fanout buffer B QA[0-9], QA[0-9] Output ECL/PECL Differential clock outputs of fanout buffer A QB[0-9], QB[0-9] Output ECL/PECL Differential clock outputs of fanout buffer B VEE (1) 1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL and PECL operation |
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Mô tả tương tự - MC100ES6220AE |
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