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ADS5270 bảng dữ liệu(PDF) 10 Page - Texas Instruments

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tên linh kiện ADS5270
Giải thích chi tiết về linh kiện  8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface
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nhà sản xuất  TI [Texas Instruments]
Trang chủ  http://www.ti.com
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ADS5270 bảng dữ liệu(HTML) 10 Page - Texas Instruments

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TEST PATTERNS
ADS5277
SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005
SERIAL INTERFACE REGISTERS
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
LVDS BUFFERS (Register 0)
All Data Outputs
0
0
Normal ADC Output
(default after reset)
0
1
Deskew Pattern
1
0
Sync Pattern
See Test Patterns
1
1
Custom Pattern
0
0
Output Current in LVDS = 3.5mA
(default after reset)
0
1
Output Current in LVDS = 2.5mA
1
0
Output Current in LVDS = 4.5mA
1
1
Output Current in LVDS = 6.0mA
0
0
0
1
CLOCK CURRENT (Register 1)
0
X
X
0
Default LVDS Clock Output Current
IOUT = 3.5mA (default)
0
X
X
1
2X LVDS Clock Output Current(1)
IOUT = 7.0mA
0
0
0
1
LSB/MSB MODE (Register 1)
0
0
X
X
LSB First Mode
(default after reset)
0
1
X
X
MSB First Mode
0
0
1
0
POWER-DOWN ADC CHANNELS
(Register 2)
X
X
X
X
Example: 1010 Powers Down
Power-Down Channels 1 to 4; D3 is
Channels 4 and 2 and
for Channel 4 and D0 for Channel 1
Keeps Channels 1 and 3 Active
0
0
1
1
POWER-DOWN ADC CHANNELS
(Register 3)
X
X
X
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (Registers 4–6)
D3
D2
D1
D0
Bits for Custom Pattern
See Test Patterns
0
1
0
0
X
X
X
X
0
1
0
1
X
X
X
X
0
1
1
0
X
X
X
X
(1)
Output current drive for the two clock LVDS buffers (LCLKP and LCLKN and ADCLKP and ADCLKN) is double the output current setting
programmed in register 0. The current drive of the data buffers remains the same as the setting in register 0.
Serial Output(1)
LSB
MSB
ADC Output(2)
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Deskew Pattern
1
0
1
0
1
0
1
0
1
0
1
0
Sync Pattern
0
0
0
0
0
0
1
1
1
1
1
1
Custom Pattern(3)
D0(4)
D1(4)
D2(4)
D3(4)
D0(5)
D1(5)
D2(5)
D3(5)
D0(6)
D1(6)
D2(6)
D3(6)
(1)
The serial output stream comes out LSB first by default.
(2)
D9...D0 represent the ten output bits from the ADC.
(3)
D0(4) represents the content of bit D0 of register 4, D3(6) represents the content of bit D3 of register 6, etc.
10


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