5

4319B–ULC–12/03

I/O Options

Inputs

Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull

up or pull down resistor.

Fast Output Buffer

Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen

option. 36mA achievable, using 2 pads.

Slew Rate Controlled Output

Buffer

In this mode, the p– and n–output transistors commands are delayed, so that they are

never set “ON” simultaneously, resulting in a low switching current and low noise. These

buffers are dedicated to very high load drive.

2.5V Compatibility

The UA1E series of ULC’s is fully capable of supporting high–performance operation at

2.5V or 3.3V. The performance specifications of any given ULC design however, must

be explicitly specified as 2.5V, 3.3V or both.

Power Supply and Noise

Protection

In order to improve the noise immunity of the UA1E core matrix, several mechanisms

have been implemented inside the UA1E arrays. Two types of protection have been

added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers

against the switching noise coming from the matrix.

The speed and density of the UA1E technology cause large switching current spikes, for

example when:

•

16 high current output buffers switch simultaneously, or

•

10% of the 700 000 gates are switching within a window of 1ns.

Sharp edges and high currents cause some parasitic elements in the packaging to

become significant. In this frequency range, the package inductance and series resis-

tance should be taken into account. It is known that an inductor slows down the setting

time of the current and causes voltage drops on the power supply lines. These drops

can affect the behavior of the circuit itself or disturb the external application (ground

bounce).

I/O Buffers Switching Protection

Three features are implemented to limit the noise generated by the switching current:

•

The power supplies of the input and output buffers are separated.

•

The rise and fall times of the output buffers can be controlled by an internal

regulator.

•

A design rule concerning the number of buffers connected on the same power

supply line has been imposed.

Matrix Switching Current

Protection

This noise disturbance is caused by a large number of gates switching simultaneously.

To allow this without impacting the functionality of the circuit, three new features have

been added:

•

Decoupling capacitors are integrated directly on the silicon to reduce the power

supply drop.

•

A power supply network has been implemented in the matrix. This solution reduces

the number of parasitic elements such as inductance and resistance and constitutes

150 cells.

•

A low pass filter has been added between the matrix and the input to the output

buffer. This limits the transmission of the noise coming from the ground or the V

DD

supply of the matrix to the external world via the output buffers.