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LM2745MTCX bảng dữ liệu(PDF) 11 Page - National Semiconductor (TI) |
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LM2745MTCX bảng dữ liệu(HTML) 11 Page - National Semiconductor (TI) |
11 / 23 page Application Information (Continued) For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the startup of the master supply and LM2745/8 output voltage was 5 ms, then the desired SD pin slew rate would be (1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for R S2 is1k Ω. To achieve the desired slew rate, R S1 would then be 274 Ω. A timing diagram for this example is shown in Figure 7. SD PIN IMPEDANCE When connecting a resistor divider to the SD pin of the LM2745/8 some care has to be taken. Once the SD voltage goes above V SD-IH, a 17 µA pull-up current is activated as shown in Figure 8. This current is used to create the internal hysteresis ()170 mV); however, high external impedances will affect the SD pin logic thresholds as well. The external impedance used for the sequencing divider network should preferably be a small fraction of the impedance of the SD pin for good performance (around 1 k Ω). MOSFET GATE DRIVERS The LM2745/8 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that unlike most other synchronous controllers, the bootstrap capacitor of the LM2745/8 provides power not only to the driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no floating driver). Two things must be kept in mind here. First, the BOOT pin has an absolute maximum rating of 18V. This must never be exceeded, even momentarily. Since the bootstrap capacitor is connected to the SW node, the peak voltage impressed on the BOOT pin is the sum of the input voltage (V IN) plus the voltage across the bootstrap capacitor (ignoring any forward drop across the bootstrap diode). The bootstrap capacitor is charged up by a given rail (called V BOOT_DC here) whenever the upper MOSFET turns off. This rail can be the same as V CC or it can be any external ground-referenced DC rail. But care has to be exercised when choosing this bootstrap DC rail that the BOOT pin is not damaged. For example, if the desired maximum V IN is 14V, and VBOOT_DC is chosen to be the same as V CC, then clearly if the VCC rail is 6V, the peak voltage on the BOOT pin is 14V + 6V = 20V. This is unac- ceptable, as it is in excess of the rating of the BOOT pin. A V CC of 3V would be acceptable in this case. Or the VIN range must be reduced accordingly. There is also the option of deriving the bootstrap DC rail from another 3V external rail, independent of V CC. The second thing to be kept in mind here is that the output of the low-side driver swings between the bootstrap DC rail level of V BOOT_DC and Ground, whereas the output of the high-side driver swings between V IN+VBOOT_DC and Ground. To keep the high-side MOSFET fully on when de- sired, the Gate pin voltage of the MOSFET must be higher than its instantaneous Source pin voltage by an amount equal to the ’Miller plateau’. It can be shown that this plateau is equal to the threshold voltage of the chosen MOSFET plus a small amount equal to Io/g. Here Io is the maximum load current of the application, and g is the transconductance of this MOSFET (typically about 100 for logic-level devices). That means we must choose V BOOT_DC to at least exceed 20137411 FIGURE 7. Delay for Sequencing 20137406 FIGURE 8. SD Pin Logic www.national.com 11 |
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