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GS71116ATP-7 bảng dữ liệu(PDF) 1 Page - List of Unclassifed Manufacturers

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GS71116ATP/J/U
64K x 16
1Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Rev: 1.07 12/2004
1/16
© 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J:
400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
GP: Pb-Free 400 mil, 3244-pin TSOP Type II package
U:
6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: Pb-Free 6 mm x 8 mm Fine Pitch Ball Grid Array
package
• Pb-Free TSOP-II and FP-BGA packages available
Description
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.
SOJ 64K x 16-Pin Configuration
Package J
Pin Descriptions
Symbol
Description
A0–A15
Address input
DQ1–DQ16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
Write enable input
OE
Output enable input
VDD
+3.3 V power supply
VSS
Ground
NC
No connect
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A4
A3
A2
A1
A0
CE
DQ1
DQ2
DQ3
DQ4
VDD
VSS
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
Top view
21
22
24
23
A12
A11
44-pin
SOJ
NC
NC


Số phần tương tự - GS71116ATP-7

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