ADS7822

10

SBAS062A

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REFERENCE INPUT

The external reference sets the analog input range. The

ADS7822 will operate with a reference in the range of 50mV

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the LSB (least significant bit) size and is equal

to the reference voltage divided by 4096. This means that any

offset or gain error inherent in the A/D converter will appear

to increase, in terms of LSB size, as the reference voltage is

reduced.

The noise inherent in the converter will also appear to

increase with lower LSB size. With a 2.5V reference, the

internal noise of the converter typically contributes only 0.32

LSB peak-to-peak of potential error to the output code. When

the external reference is 50mV, the potential error contribu-

tion from the internal noise will be 50 times larger—16

LSBs. The errors due to the internal noise are gaussian in

nature and can be reduced by averaging consecutive conver-

sion results.

For more information regarding noise, consult the typical

performance curves “Effective Number of Bits vs Reference

Voltage” and “Peak-to-Peak Noise vs Reference Voltage.”

Note that the effective number of bits (ENOB) figure is

calculated based on the converter’s signal-to-(noise + distor-

tion) ratio with a 1kHz, 0dB input signal. SINAD is related

to ENOB as follows

SINAD = 6.02 • ENOB + 1.76

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter will also

be more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

DIGITAL INTERFACE

SIGNAL LEVELS

The digital inputs of the ADS7822 can accommodate logic

ADS7822 can be powered at 3V and still accept inputs from

logic powered at 5V.

input, then that IC may require more supply current than

normal and may have a slightly longer propagation delay.

SERIAL INTERFACE

The ADS7822 communicates with microprocessors and other

digital systems via a synchronous 3-wire serial interface as

shown in Figure 1 and Table I. The DCLOCK signal syn-

chronizes the data transfer with each bit being transmitted on

the falling edge of DCLOCK. Most receiving systems will

capture the bitstream on the rising edge of DCLOCK. How-

system can use the falling edge of DCLOCK to capture each

bit.

FIGURE 1. ADS7822 Basic Timing Diagrams.

CS/SHDN

D

OUT

DCLOCK

t

DATA

t

SUCS

t

CYC

t

CONV

Power

Down

t

SMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS

LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.

B11

(MSB)

B10 B9

B8

B7

B6

B5

B4

B3

B2

Null

Bit

Hi-Z

Hi-Z

B11 B10

B9

B8

Null

Bit

CS/SHDN

D

OUT

DCLOCK

t

CONV

t

DATA

t

SUCS

t

CSD

t

CYC

Power Down

t

SMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS

LOW, the A/D will output zeroes indefinitely.

t

becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

B11

(MSB)

B10 B9

B8

B7

B6

B5

B4

B4

B3

B3

B2

B2

B1

B1

B0

Null

Bit

Hi-Z

Hi-Z

B5

B6

B7

B8

B9

B10 B11

(1)

t

CSD