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MAX9424 bảng dữ liệu(PDF) 5 Page - Maxim Integrated Products |
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MAX9424 bảng dữ liệu(HTML) 5 Page - Maxim Integrated Products |
5 / 11 page Lowest Jitter Quad PECL-to-ECL Differential Translators _______________________________________________________________________________________ 5 Pin Description PIN NAME FUNCTION 1, 8 VCC Positive Supply Voltage. Bypass VCC to VGG with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2 SEL Noninverting Differential Select Input. Setting SEL = 1 and SEL = 0 enables all four channels to operate independently. Setting SEL = 0 and SEL = 1 enables all four channels to be synchronized to CLK. 3 SEL Inverting Differential Select Input 4 CLK Noninverting Differential Clock Input 5 CLK Inverting Differential Clock Input 6EN Noninverting Differential Output Enable Input. Setting EN = 1 and EN = 0 enables all four outputs. Setting EN = 0 and EN = 1 disables all four outputs. 7 EN Inverting Differential Output Enable Input 9 IN3 Noninverting Differential Input 3 10 IN3 Inverting Differential Input 3 11, 17, 24, 30 VGG Ground Reference 12 OUT3 Inverting Differential Output 3 13 OUT3 Noninverting Differential Output 3 14, 20, 21, 27 VEE Negative Supply Voltage. Bypass from VEE to VGG with 0.1µF and 0.01µF ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 15 IN2 Noninverting Differential Input 2 16 IN2 Inverting Differential Input 2 18 OUT2 Inverting Differential Output 2 19 OUT2 Noninverting Differential Output 2 22 OUT1 Noninverting Differential Output 1 23 OUT1 Inverting Differential Output 1 25 IN1 Inverting Differential Input 1 26 IN1 Noninverting Differential Input 1 28 OUT0 Noninverting Differential Output 0 29 OUT0 Inverting Differential Output 0 31 IN0 Inverting Differential Input 0 32 IN0 Noninverting Differential Input 0 |
Số phần tương tự - MAX9424 |
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Mô tả tương tự - MAX9424 |
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