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PE310G4SPI9LA Datasheet(PDF) 2 Page - Silicom Ltd. |
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Silicom Ltd. Connectivity Solutions Page 2 Host Interface: PCI Express X8 lanes Support PCI Express Base Specification 3.0 (8GT/sec) Low power Performance Features: IPV4 and IPV6 Supports for IP/ TCP and IP/UDP Receive Checksum offload Fragmented UDP checksum offload for Packet Reassembly CPU utilization- the 82599 supports reduction in CPU utilization, mainly by supporting Receive Side Coalescing (RSC) Support for 16 virtual machine Device Queues (VMDq) per port Support Direct Cache Access (DCA) Advanced memory architecture reduces latency by preceding TSO packets. A TSO packet may be interleaved with other packets going to the wire Minimized device I/O intterupts using MSI and MSI-X Offload of TCP / IP / UDP checksum calculation and TCP segmentation Large on chip receive packet buffer (512 KB) Large on chip transmit packet buffer (160KB) Supports the VPD (Vital Product Data) capability defined in the PCI specification ver. 3.0 Time sync- IEEE1588- Precision Time Protocol (PTP) Supports the BCN (Backward Congestion Notification) protocol in addition to the EEDC functionality LAN Features: IEEE 802.x flow control support IEEE 802.q VLAN tagging support Supports a mode where all received and sent packets have at least one VLAN tag in addition to the regular tagging IEEE 802.1p layer 2 priority encoding Jumbo Frame (up to 15.5KB) Link Aggregation and Load Balancing RFC2819 RMON MIB statistics TCP Segmentation Offload Up to 256KB Ipv6 Support for IP/TCP Receive Checksum Offload DDP Offload LEDs indicators for link/Activity and speed |
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