74ALVCHS162830A

1BIT TO 2BIT ADDRESS DRIVER

WITH 3STATE OUTPUTS

SCES624 − FEBRUARY 2005

5

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

VM

VM

VM

VM

VM

VM

VM

VM

VOH

VOL

th

tsu

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

S1

Open

GND

RL

RL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at VLOAD

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

0 V

VOL + V∆

VOH − V∆

0 V

VI

0 V

0 V

tw

VI

VI

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

VLOAD

GND

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω.

D. The outputs are measured one at a time, with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

0 V

VI

VM

tPHL

VM

VM

VI

0 V

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VM

VM

tPLH

VLOAD

VLOAD/2

2.5 V

± 0.2 V

2.7 V

3.3 V

± 0.3 V

500

Ω

500

Ω

500

Ω

VCC

RL

2

× VCC

6 V

6 V

VLOAD

CL

30 pF

50 pF

50 pF

0.15 V

0.3 V

0.3 V

V∆

VCC

2.7 V

2.7 V

VI

VCC/2

1.5 V

1.5 V

VM

tr/tf

≤2 ns

≤2.5 ns

≤2.5 ns

INPUT

Figure 1. Load Circuit and Voltage Waveforms