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AD10226 bảng dữ liệu(PDF) 5 Page - Analog Devices |
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AD10226 bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 20 page REV. 0 AD10226 –5– PIN CONFIGURATION 35mm SQUARE BOTTOM VIEW A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 24 22 20 18 16 14 12 10 8 6 4 2 25 23 21 19 17 15 13 11 9 7 5 3 1 PIN FUNCTION DESCRIPTIONS Mnemonic Function AGNDA A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. REF_A_OUT A Channel Internal Voltage Reference NC No connection AIN A1 Analog Input for A side ADC (– input) AIN A2 Analog Input for A side ADC (+ input) AVCCA Analog Positive Supply Voltage (nominally 5.0 V) DGNDA A Channel Digital Ground D11A–D0A Digital Outputs for ADC A. D0 (LSB) ENCODEA Complement of ENCODE ENCODEA Data conversion initiated on the rising edge of ENCODE input. DVCCA Digital Positive Supply Voltage (nominally 3.3 V) DGNDB B Channel Digital Ground D11B–D0B Digital Outputs for ADC B. D0 (LSB) AGNDB B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. DVCCB Digital Positive Supply Voltage (nominally 3.3 V) ENCODEB Complement of ENCODE ENCODEB Data conversion initiated on rising edge of ENCODE input. REF_B_OUT B Channel Internal Voltage Reference AIN B1 Analog Input for B side ADC (– input) AIN B2 Analog Input for B side ADC (+ input) AVCCB Analog Positive Supply Voltage (nominally 5.0 V) DFS Data format select. Low = Two’s Complement, High = Binary. SFDR Mode CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation. |
Số phần tương tự - AD10226 |
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Mô tả tương tự - AD10226 |
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