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TMUX1208-Q1 bảng dữ liệu(PDF) 22 Page - Texas Instruments

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tên linh kiện TMUX1208-Q1
Giải thích chi tiết về linh kiện  TMUX1208-Q1 5-V Bidirectional 8:1 Multiplexer with 1.8-V Logic
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10 Layout
10.1 Layout Guidelines
10.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 10-1 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
1W min.
W
Figure 10-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
10.1.2
Figure 10-2 illustrates an example of a PCB layout with the TMUX1208-Q1. Some key considerations are:
• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
A0
EN
N.C.
S1
S2
S3
A1
A2
GND
VDD
S5
S6
S4
Via to
grou nd plane
TMUX120 8-Q1
C
S8
D
S7
Wide (low inductance)
trace for power
Via to
grou nd plane
Figure 10-2. TMUX1208-Q1 Layout Example
TMUX1208-Q1
SCDS415A – AUGUST 2019 – REVISED JULY 2020
www.ti.com
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