9.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will

voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output

Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected

directly together. This can cause excessive current and damage to the device.

Two channels within the same device with the same input signals can be connected in parallel for additional

output drive strength.

Refer to Feature Description section for additional information regarding the outputs for this device.

9.2.2 Detailed Design Procedure

section.

2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal

performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS595

to the receiving device(s).

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

SER

SRCLK rising edge shifts data

in the serial registers only

SER

RCLK rising edge shifts data

to the output registers

Figure 9-2. Simplified functional diagram showing clock operation

SN74HCS595

SCLS803 – AUGUST 2020

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