10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps

to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The

bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in

given example layout image.

11 Layout

11.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many

cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a

triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left

unconnected because the undefined voltages at the outside connections result in undefined operational states.

All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the

input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular

makes more sense for the logic function or is more convenient.

11.2 Layout Example

1

2

3

4

5

6

7

16

15

14

13

12

11

10

S0

S1

Q0

Q2

GND

G

Q7

Q6

GND

D

S2

0.1

F

Bypass capacitor

placed close to the

device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused

output left

floating

Q3

Q4

8

9

Q5

CLR

Q1

Figure 11-1. Example layout for the SN74HCS259-Q1 in the PW package.

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SN74HCS259-Q1

SCLS815 – JULY 2020

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