9.3 Typical Application

SN74AVC(H)24T245

1OE/2OE/3OE/

4OE/5OE/6OE

1DIR/2DIR/3DIR/

4DIR/5DIR/6DIR

1A1/1A2/1A3/1A4

1.8-V

Controller

VCCA

VCCB

1B1/1B2/1B3/1B4

3.3-V

System

1.8 V

3.3 V

GND

GND

GND

Data

Data

2A1/2A2/2A3/2A4

3A1/3A2/3A3/3A4

4A1/4A2/4A3/4A4

5A1/5A2/5A3/5A4

6A1/6A2/6A3/6A4

2B1/2B2/2B3/2B4

3B1/3B2/3B3/3B4

4B1/4B2/4B3/4B4

5B1/5B2/5B3/5B4

6B1/6B2/6B3/6B4

0.1 µF

0.1 µF

Figure 9-1. Application Schematic

9.3.1 Design Requirements

This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the

intended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must not

be floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input and

output ports directly to ground.

For this design example, use the parameters listed in the Electrical Characteristics.

Table 9-1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

1.2 V to 3.6 V

Output voltage range

1.2 V to 3.6 V

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SN74AVC24T245

SCES552E – FEBRUARY 2004 – REVISED AUGUST 2020

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