24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-

State Outputs

1 Features

GND, All Outputs Are in the High-Impedance State

• Overvoltage-Tolerant Inputs/Outputs Allow Mixed-

Voltage-Mode Data Communications

• Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over Full 1.2-V to 3.6-V Power-

Supply Range

• I/Os Are 4.6-V Tolerant

• Max Data Rates

– 380 Mbps (1.8-V to 3.3-V Translation)

– 200 Mbps (<1.8-V to 3.3-V Translation)

– 200 Mbps (Translate to 2.5 V or 1.8 V)

– 150 Mbps (Translate to 1.5 V)

– 100 Mbps (Translate to 1.2 V)

• Latch-Up Performance Exceeds 100 mA Per JESD

78, Class II

• ESD Protection Exceeds JESD 22

– 8000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2 Applications

• Personal Electronics

• Industrial

• Enterprise

• Telecom

3 Description

This 24-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The

accepts any supply voltage from 1.2 V to 3.6 V. This

allows for universal low-voltage bidirectional

translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-

V, and 3.3-V voltage nodes.

The SN74AVC24T245 is designed for asynchronous

communication between data buses. The device

transmits data from the A bus to the B bus or from the

B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable ( OE)

input can be used to disable the outputs so the buses

are effectively isolated.

The SN74AVC24T245 is designed so that the control

pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1 OE, 2

OE, 3 OE, 4 OE, 5 OE, and 6 OE) are supplied by

This device is fully specified for partial-power-down

outputs, preventing damaging current backflow

through the device when it is powered down.

input is at GND, then both ports are in the high-

impedance state.

To ensure the high-impedance state during power up

pullup resistor; the minimum value of the resistor is

determined by the current-sinking capability of the

driver.

Device Information

PART NUMBER

PACKAGE(1)

BODY SIZE (NOM)

SN74AVC24T245GRG/ZRG LFBGA

10.00 mm × 4.50

mm

SN74AVC24T245NMU

nFBGA

10.00 mm × 4.50

mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

To Three Other Channels

1DIR

1A1

1B1

1OE

To Three Other Channels

2DIR

2A1

2B1

2OE

P6

B6

P5

D6

A6

B1

A5

D1

To Three Other Channels

3DIR

3A1

3B1

3OE

To Three Other Channels

4DIR

4A1

4B1

4OE

P4

F6

P3

H6

A4

F1

A3

H1

To Three Other Channels

5DIR

5A1

5B1

5OE

To Three Other Channels

6DIR

6A1

6B1

6OE

P2

K6

P1

M6

A2

K1

A1

M1

Figure 3-1. Logic Diagram

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SN74AVC24T245

SCES552E – FEBRUARY 2004 – REVISED AUGUST 2020

Copyright © 2020 Texas Instruments Incorporated

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SN74AVC24T245

SCES552E – FEBRUARY 2004 – REVISED AUGUST 2020

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.