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RM48L940 bảng dữ liệu(PDF) 16 Page - Texas Instruments |
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RM48L940 bảng dữ liệu(HTML) 16 Page - Texas Instruments |
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16 / 174 page  RM48L940, RM48L740, RM48L540 SPNS175C – APRIL 2012 – REVISED JUNE 2015 www.ti.com 4.3.1.9 Multibuffered Serial Peripheral Interface Modules (MibSPI) Table 4-9. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI) TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION 144 TYPE SIGNAL NAME STATE PGE MIBSPI1CLK 95 MibSPI1 clock, or GPIO MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 Programmable, Pullup 20 µA MIBSPI1NCS[1]/N2HET1[17]/MII_COL 130 MibSPI1 chip select, or GPIO MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 N2HET1[15]/MIBSPI1NCS[4] 41 Programmable, Pulldown MibSPI1 chip select, or GPIO 20 µA N2HET1[24]/MIBSPI1NCS[5]/MII_RXD[0]/RMII_RXD[0] 91 I/O MIBSPI1NENA/N2HET1[23]/MII_RXD[2] 96 MibSPI1 enable, or GPIO Programmable, Pullup 20 µA MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GPIO Programmable, N2HET1[8]/MIBSPI1SIMO[1]/MII_TXD[3] 106 Pulldown MibSPI1 slave-in master-out, or GPIO 20 µA MIBSPI1SOMI[0] 94 Programmable, Pullup MibSPI1 slave-out master-in, or GPIO 20 µA MIBSPI1NCS[0]/MIBSPI1SOMI[1]/MII_TXD[2] 105 MIBSPI3CLK 53 MibSPI3 clock, or GPIO MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Pullup 20 µA MibSPI3 chip select, or GPIO MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Programmable, N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Pulldown MibSPI3 chip select, or GPIO 20 µA MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 chip select, or GPIO MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 enable, or GPIO Programmable, Pullup 20 µA MIBSPI3SIMO[0] 52 MibSPI3 slave-in master-out, or GPIO MIBSPI3SOMI[0] 51 MibSPI3 slave-out master-in, or GPIO MIBSPI5CLK/MII_TXEN/RMII_TXEN 100 MibSPI5 clock, or GPIO MIBSPI5NCS[0] 32 MibSPI5 chip select, or GPIO Programmable, MIBSPI5NENA/MII_RXD[3] 97 I/O Pullup MibSPI5 enable, or GPIO 20 µA MIBSPI5SIMO[0]/MII_TXD[1]/RMII_TXD[1] 99 MibSPI5 slave-in master-out, or GPIO MIBSPI5SOMI[0]/MII_TXD[0]/RMII_TXD[0] 98 MibSPI5 slave-out master-in, or GPIO 4.3.1.10 Ethernet Controller Table 4-10. PGE Ethernet Controller: MDIO Interface TERMINAL RESET SIGNAL PULL PULL TYPE DESCRIPTION 144 TYPE SIGNAL NAME STATE PGE Programmable, MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 Output Pullup Serial clock output 20 µA Fixed 20-µA MIBSPI1NCS[2]/N2HET1[19]/MDIO 40 I/O Pullup Serial data input/output Pullup 16 Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback |
Số phần tương tự - RM48L940_V01 |
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Mô tả tương tự - RM48L940_V01 |
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