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RM48L940 bảng dữ liệu(PDF) 85 Page - Texas Instruments |
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RM48L940 bảng dữ liệu(HTML) 85 Page - Texas Instruments |
85 / 174 page RM48L940, RM48L740, RM48L540 www.ti.com SPNS175C – APRIL 2012 – REVISED JUNE 2015 6.13.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized to zero through the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC). The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized. For more information on these registers see the device specific technical reference manual. The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-26. Table 6-26. Memory Initialization ADDRESS RANGE MSINENA REGISTER CONNECTING MODULE BIT NO. BASE ADDRESS ENDING ADDRESS RAM (PD#1) 0x08000000 0x0800FFFF 0(1) RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1) RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1) RAM (RAM_PD#3)(2) 0x08030000 0x0803FFFF 0(1) MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(3) MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(3) MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(3) DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET2 RAM 0xFF440000 0xFF45FFFF 15 N2HET1 RAM 0xFF460000 0xFF47FFFF 3 HTU2 RAM 0xFF4C0000 0xFF4DFFFF 16 HTU1 RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 Ethernet RAM (CPPI Memory 0xFC520000 0xFC521FFF n/a Slave) (1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized. (2) Not available on theRM48L540 device. (3) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the module is released from its local reset via the SPIGCR0 register. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. Before the MibSPI RAM can be initialized using the system module auto-initialization method: (I) The module must be released from its local reset, AND (ii) The application must poll for the "BUF INIT ACTIVE" status flag in the SPIFLG register to become cleared (zero) Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 85 Submit Documentation Feedback |
Số phần tương tự - RM48L940_V01 |
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Mô tả tương tự - RM48L940_V01 |
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