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RM48L940 bảng dữ liệu(PDF) 67 Page - Texas Instruments |
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RM48L940 bảng dữ liệu(HTML) 67 Page - Texas Instruments |
67 / 174 page RM48L940, RM48L740, RM48L540 www.ti.com SPNS175C – APRIL 2012 – REVISED JUNE 2015 6.6.3 Clock Test Mode The RM4x platform architecture defines a special mode that allows various clock signals to be brought out on to the ECLK pin and N2HET1[12] device outputs. This mode is called the Clock Test mode. It is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. Table 6-14. Clock Test Mode Options SEL_ECP_PIN SEL_GIO_PIN = SIGNAL ON ECLK = SIGNAL ON N2HET1[12] CLKTEST[3-0] CLKTEST[11-8] 0000 Oscillator 0000 Oscillator Valid Status 0001 Main PLL free-running clock output 0001 Main PLL Valid status 0010 Reserved 0010 Reserved 0011 EXTCLKIN1 0011 Reserved 0100 CLK80K 0100 Reserved 0101 CLK10M 0101 CLK10M Valid status 0110 Secondary PLL free-running clock output 0110 Secondary PLL Valid Status 0111 EXTCLKIN2 0111 Reserved 1000 GCLK 1000 CLK80K 1001 RTI Base 1001 Reserved 1010 Reserved 1010 Reserved 1011 VCLKA1 1011 Reserved 1100 Reserved 1100 Reserved 1101 VCLKA3 1101 Reserved 1110 VCLKA4 1110 Reserved 1111 Reserved 1111 Reserved Copyright © 2012–2015, Texas Instruments Incorporated System Information and Electrical Specifications 67 Submit Documentation Feedback |
Số phần tương tự - RM48L940_V01 |
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Mô tả tương tự - RM48L940_V01 |
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