LMK61E08 datasheet(20/54 Pages) TI

tên linh kiện	LMK61E08

Giải thích chi tiết về linh kiện	LMK61E08 Ultra-Low Jitter Programmable Oscillator With Internal EEPROM

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Device Registers

Device

Hardware

EEPROM

SRAM

SCL

SDA

I2C

Port

Device

Control

And

Status

Reg 0

Reg1

Reg2

Reg3

Reg32

Reg33

Reg34

Reg35

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20

LMK61E08

SNAS805 – JUNE 2020

www.ti.com

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Device Functional Modes (continued)

Figure 26. LMK61E08 Interface and Control Block

8.4.2 DCXO Mode and Frequency Margining

8.4.2.1 DCXO Mode

In applications that require the LMK61E08 as part of a PLL that is implemented in another device like an FPGA,

it can be used as a digitally-controlled oscillator (DCXO) where the frequency control word can be passed along

through I2C to the LMK61E08 on a regular basis, which in turn updates the numerator of its fractional feedback

divider by the required amount. In such a scenario, the entire portion of numerator for the fractional feedback

divider must be written on every attempt MSB first and LSB last to ensure that the output frequency does not

jump during the update, as described in Feedback Divider (N). In every update cycle, a total of 46 bits needs to

be updated leading to a maximum update rate of 8.7 kHz with a maximum I2C rate of 1 Mbps. The minimum step

size of 0.55 ppb (parts per billion) is achieved for the maximum VCO frequency of 5.6 GHz and when reference

input doubler is disabled and reference divider is set to 4. The minimum step size of 4.96 ppb (parts per billion) is

achieved for the maximum VCO frequency of 4.8 GHz and when reference input doubler is enabled and

reference divider is bypassed.

Số phần tương tự - LMK61E08

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