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DRV8889-Q1 bảng dữ liệu(PDF) 69 Page - Texas Instruments |
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DRV8889-Q1 bảng dữ liệu(HTML) 69 Page - Texas Instruments |
69 / 88 page 10 Layout 10.1 Layout Guidelines The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin. The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an electrolytic capacitor. A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for VM is recommended. Place this component as close to the pins as possible. A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16 V is recommended. Place this component as close to the pins as possible. Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is recommended. Place this bypassing capacitor as close to the pin as possible. The thermal PAD must be connected to system ground. www.ti.com DRV8889-Q1 SLVSEE9C – APRIL 2020 – REVISED AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: DRV8889-Q1 |
Số phần tương tự - DRV8889-Q1_V02 |
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Mô tả tương tự - DRV8889-Q1_V02 |
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