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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DRV8353M bảng dữ liệu(PDF) 25 Page - Texas Instruments |
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DRV8353M bảng dữ liệu(HTML) 25 Page - Texas Instruments |
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25 / 76 page  IDRIVE MODE GAIN VDS R GAIN DVDD DVDD DVDD DVDD DVDD DVDD R VDS Hardware Interface Figure 13-9. Hardware Interface 13.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect to VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions. The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required between the CPH and CPL pins to act as the flying capacitor. VDRAIN VCP 1 …F CPH Charge Pump Control VM CPL 47 nF VDRAIN Figure 13-10. Charge Pump Architecture The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is www.ti.com DRV8353M SLVSFO2 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DRV8353M |
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