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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DRV8353M bảng dữ liệu(PDF) 37 Page - Texas Instruments |
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DRV8353M bảng dữ liệu(HTML) 37 Page - Texas Instruments |
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37 / 76 page  50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to minimize the amplifier input offset. After this the amplifiers are ready for normal operation. For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain setting in order to improve the accuracy of the calibration routine. 13.3.4.4 MOSFET VDS Sense Mode (SPI Only) The current-sense amplifiers on the DRV8353M SPI devices can be configured to amplify the voltage across the external low-side MOSFET VDS. This allows for the external controller to measure the voltage drop across the MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level. To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side MOSFET as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the negative reference for the low-side VDS monitor is automatically set to SNx, regardless of the state of the LS_REF bit state. This setting is implemented to prevent disabling of the low-side VDS monitor. If the system operates in MOSFET VDS sensing mode, route the SHx and SNx pins with Kelvin connections across the drain and source of the external low-side MOSFETs. GHx SHx GLx GND VDRAIN SNx SPx AV SOx 0 1 CSA_FET = 0 LS_REF = 0 (SPI only) VDRAIN + VDS Low-Side VDS Monitor + VDS High-Side VDS Monitor 10 k 10 k 10 k ± ± RSEN VCP VGLS Figure 13-28. Resistor Sense Configuration www.ti.com DRV8353M SLVSFO2 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DRV8353M |
Số phần tương tự - DRV8353M |
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Mô tả tương tự - DRV8353M |
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