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BQ24160 bảng dữ liệu(PDF) 26 Page - Texas Instruments |
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BQ24160 bảng dữ liệu(HTML) 26 Page - Texas Instruments |
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26 / 53 page  DATA CLK START Condition STOP Condition S P 26 bq24160, bq24160A, bq24161 bq24161B, bq24163, bq24168 SLUSAO0G – NOVEMBER 2011 – REVISED DECEMBER 2015 www.ti.com Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated 9.4 Device Functional Modes The state machine of the bq2416x automatically changes primary states (Off, sleep, HiZ, charge disabled, charging, charge done, battery OVP, fault) based on data in the I2C registers, IN and USB pin voltages, BAT pin voltage and current flow, TS pin voltage, CD pin voltage and status of the safety timer. The BAT and TS pin voltages as well as current flow into the IN and USB pins, out of SYS pin and into/out of the BAT pin determine the charging sub-states, including conditioning, constant current (CC), CC with reduced charge current, constant voltage (CV) with reduced charge current. 9.5 Programming 9.5.1 Serial Interface Description The bq2416xx uses an I2C-compatible interface to program charge parameters. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All I2C-compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The bq2416xx device works as a slave and supports the following data transfer modes, as defined in the I2C Bus Specification: standard mode (100kbps) and fast mode (400kbps). The interface adds flexibility to the battery charging solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as battery voltage remains above 2.5V (typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is not connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V with no input connected in order to maintain proper operation. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The bq2416xx devices only support 7-bit addressing. The device 7-bit address is defined as ‘1101011’ (6Bh). 9.5.1.1 F/S Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 17. All I2C-compatible devices should recognize a start condition. Figure 17. START and STOP Condition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 18). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 19) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. |
Số phần tương tự - BQ24160_V01 |
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Mô tả tương tự - BQ24160_V01 |
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