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AWR2243 bảng dữ liệu(PDF) 41 Page - Texas Instruments |
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AWR2243 bảng dữ liệu(HTML) 41 Page - Texas Instruments |
41 / 62 page 10 Monitoring and Diagnostic Mechanisms Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR2243 Table 10-1. Monitoring and Diagnostic Mechanisms for AWR2243 S No Feature Description 1 Boot time LBIST For Master R4F Core and associated VIM AWR2243 architecture supports hardware logic BIST (LBIST) engine self-test Controller (STC). This logic is used to provide a very high diagnostic coverage (>90%) on the Master R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level. LBIST for the CPU and VIM are triggered by the bootloader. 2 Boot time PBIST for Master R4F TCM Memories Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and TCMB1. AWR2243 architecture supports a hardware programmable memory BIST (PBIST) engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the implemented Master R4F TCMs at a transistor level. PBIST for TCM memories is triggered by Bootloader at the boot time . CPU stays there in while loop and does not proceed further if a fault is identified. 3 End to End ECC for Master R4F TCM Memories TCMs diagnostic is supported by Single error correction double error detection (SECDED) ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64- bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU is configured to have predetermined response (Ignore or Abort generation) to single and double bit error conditions. 4 Master R4F TCM bit multiplexing Logical TCM word and its associated ECC code is split and stored in two physical SRAM banks. This scheme provides an inherent diagnostic mechanism for address decode failures in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an ECC fault.Further, bit multiplexing scheme implemented such that the bits accessed to generate a logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word, this scheme improves the usefulness of the TCM ECC diagnostic. 5 Clock Monitor AWR2243 architecture supports Three Digital Clock Comparators (DCCs) and an internal RCOSC. Dual functionality is provided by these modules – Clock detection and Clock Monitoring. DCCint is used to check the availability/range of Reference clock at boot otherwise the device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This provides debug capability). DCCint is only used by boot loader during boot time. It is disabled once the APLL is enabled and locked. DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided version with the Reference input clock of the device. Initially (before configuring APLL), DCC1 is used by bootloader to identify the precise frequency of reference input clock against the internal RCOSC clock source. Failure detection for DCC1 would cause the device to go into limp mode. Clock Compare module (CCC) module is used to compare the APLL divided down frequency with reference clock (XTAL). Failure detection is indicated by the nERROR OUT signal. 6 RTI/WD for Master R4F Internal watchdog is enabled by the bootloader in a windowed watchdog (DWWD) mode.. Watchdog expiry issues an internal warm reset and nERROR OUT signal to the host. 7 MPU for Master R4F Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial separation of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It is expected that the operating system controls the MPU and changes the MPU settings based on the needs of each task. A violation of a configured memory protection policy results in a CPU abort. 8 PBIST for Peripheral interface SRAMs - SPI, I2C AWR2243 architecture supports a hardware programmable memory BIST (PBIST) engine for Peripheral SRAMs as well. PBIST for peripheral SRAM memories is triggered by the bootloader. The PBIST tests are destructive to memory contents, and as such are typically run only at boot time. . Any fault detected by the PBIST results in an error indicated in PBIST and boot status response message. 9 ECC for Peripheral interface SRAMs – SPI, I2C Peripheral interface SRAMs diagnostic is supported by Single error correction double error detection (SECDED) ECC diagnostic. When a single or double bit error is detected the error is indicated by nERROR (double bit error) or via SPI message (single bit error). 10 Cyclic Redundancy Check – Master SS Cyclic Redundancy Check (CRC) module is available for the Master SS. The firmware uses this feature for data transfer checks in mailbox and SPI communication. www.ti.com AWR2243 SWRS223A – FEBRUARY 2020 – REVISED AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: AWR2243 |
Số phần tương tự - AWR2243_V01 |
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Mô tả tương tự - AWR2243_V01 |
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