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57 / 89 page Electrical characteristics i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020 NXP Semiconductors 57 Figure 34. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1, 0x2 NOTE Timing shown is based on the memory generating read data on the SCK falling edge, and FlexSPI controller sampling read data on the falling edge. 3.9.9.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3 There are two cases when the memory provides both read data and the read strobe in SDR mode: •A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge) •A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising edge Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1, 0x2 Symbol Parameter Min. Max. Unit Notes — [D:] Frequency of operation — 133 MHz — F1 [D:] Setup time for incoming data 1.5 — ns 1 1 The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be decreased by up to 2ns. F2 [D:] Hold time for incoming data 1 — ns — Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1) Symbol Parameter Min. Max. Unit — [D:] Frequency of operation — 166 MHz F3 [D:] Time from SCK to data valid — — ns F4 [D:] Time from SCK to DQS — — ns — [D:] Time delta between TSCKD and TSCKDQS -2 2 ns F1 F2 F1 F2 FLEXSPI_SCLK FLEXSPI_DATA[7:0] Internal Sample Clock |
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