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48 / 89 page  i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020 48 NXP Semiconductors Electrical characteristics In EDO mode (Figure 24), NF16/NF17 are different from the definition in non-EDO mode (Figure 23). They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Nano Applications Processor Reference Manual [IMX8MNRM]). The typical value of this control register is 0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. Table 39. Asynchronous mode timing parameters1 1 GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min. Max. NF1 NAND_CLE setup time tCLS (AS + DS) T - 0.12 [see notes2,3] 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075 ns (half of maximum p-p jitter). ns NF2 NAND_CLE hold time tCLH DH T - 0.72 [see note2]ns NF3 NAND_CE0_B setup time tCS (AS + DS + 1) T [see notes3,2]ns NF4 NAND_CE0_B hold time tCH (DH+1) T - 1 [see note2]ns NF5 NAND_WE_B pulse width tWP DS T [see note2]ns NF6 NAND_ALE setup time tALS (AS + DS) T - 0.49 [see notes3,2]ns NF7 NAND_ALE hold time tALH DH T - 0.42 [see note2]ns NF8 Data setup time tDS DH T - 0.26 [see note2]ns NF9 Data hold time tDH DH T - 1.37 [see note2]ns NF10 Write cycle time tWC (DS + DH) T [see note2]ns NF11 NAND_WE_B hold time tWH DH T [see note2]ns NF12 Ready to NAND_RE_B low tRR4 4 NF12 is guaranteed by the design. (AS + 2) T [see 3,2]— ns NF13 NAND_RE_B pulse width tRP DS T [see note2]ns NF14 READ cycle time tRC (DS + DH) T [see note2]ns NF15 NAND_RE_B high hold time tREH DS T [see note2]ns NF16 Data setup on read tDSR — (DS T -0.67)/18.38 [see notes5,6] 5 Non-EDO mode. 6 EDO mode, GPMI clock 100 MHz (AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). ns NF17 Data hold on read tDHR 0.82/11.83 [see notes5,6]— ns |
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