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i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020
40
NXP Semiconductors
Electrical characteristics
3.9.2.4
HS200 Mode AC timing
Figure 15 depicts the timing of HS200 mode, and Table 34 lists the HS200 timing characteristics.
Figure 15. HS200 timing
iti
SD6
uSDHC input skew
tRQ
—0.45
ns
SD7
uSDHC hold skew
tRQH
—0.45
ns
Table 34. HS200 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
5.0
ns
SD2
Clock Low Time
tCL
0.3 x tCLK
0.7 x tCLK
ns
SD3
Clock High Time
tCH
0.3 x tCLK
0.7 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
-1.6
1
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)1
1 HS200 is for 8 bits while SDR104 is for 4 bits.
SD8
uSDHC Output Data Window
tODW
0.5 x tCLK
—ns
Table 33. HS400 interface timing specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
SCK
8-bit output from uSDHC to eMMC
8-bit input from eMMC to uSDHC
SD8
SD4/SD5
SD2
SD3
SD1


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