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JN5189 bảng dữ liệu(PDF) 56 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  IEEE 802.15.4 low power wireless MCU
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JN5189 bảng dữ liệu(HTML) 56 Page - NXP Semiconductors

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JN5189
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1.2 — June 2020
56 of 92
NXP Semiconductors
IEEE 802.15.4 low power wireless MCU
JN5189(T)/JN5188(T)
[1]
Assumes internal pull-up resistor value of 100 k
 worst case and 5 pF external capacitance.
[2]
Minimum voltage to avoid being reset.
[3]
Device setting from reset
14.1.2 Analog to Digital Converters
[1]
With x = 0, 1, 2, 3, 4, or 5.
Vhys
Hysteresis voltage
Supply voltage (VBAT)
monitor; configurable in 4
levels
18.75
25
31.25
mV
37.50
50
62.5
mV
56.25
75
93.75
mV
[3]
75.00
100
125
mV
Table 18.
Externally applied reset …continued
VDDE = 1.9 V to 3.6 V, Tj = -40 °C to +125 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Fig 11. Reset signal timing
tSTAB
Vrh
trst
Vrl
internal RESET
RST_IN
tSTAB
Table 19.
Analog to Digital Converters
VDDE = 1.9 V to 3.6 V; Tj = -40
°C to +125 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vi
Input voltage
switchable
0
VBAT
V
FSR
Full scale range
After calibration
3.56
3.6
3.62
IADCx
Current on pins ADCx[1]
100
A
INL
Integral non-linearity
1.1
LSB
DNL
Differential non-linearity
0.85
LSB
EO
Offset error
After calibration
-4.5
4.5
mV
EG
Gain error
After calibration
-40
0
20
mV
fS
Sampling frequency
Single channel
78.4
100
190
ksps
tconv
Conversion time
10
s
Ci(a)
Analog input
capacitance
4
pF
SFDR
Spurious-free dynamic
range
For Fin = 25 kHz
75
dBc


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